ATTINY85-20SU Atmel, ATTINY85-20SU Datasheet - Page 141
![IC AVR MCU 8K 20MHZ 8SOIC](/photos/6/50/65032/453-8-soic_sml.jpg)
ATTINY85-20SU
Manufacturer Part Number
ATTINY85-20SU
Description
IC AVR MCU 8K 20MHZ 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY85-20SU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY85-20SU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 141 of 236
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17.13.3
17.13.3.1
17.13.3.2
17.13.4
2586M–AVR–07/10
ADCL and ADCH – The ADC Data Register
ADCSRB – ADC Control and Status Register B
ADLAR = 0
ADLAR = 1
Table 17-5.
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• Bits 9:0 - ADC[9:0]: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page
• Bit 7 – BIN: Bipolar Input Mode
The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected
by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided conversions
Bit
0x05
0x04
Read/Write
Initial Value
Bit
0x05
0x04
Read/Write
Initial Value
Bit
0x03
Read/Write
Initial Value
136.
ADPS2
1
1
1
ADC Prescaler Selections (Continued)
ADC7
ADC9
ADC1
R/W
BIN
15
15
R
R
R
R
–
7
0
0
7
0
0
7
0
ADC6
ADC8
ADC0
ACME
R/W
14
14
ADPS1
R
R
R
R
–
6
0
0
6
0
0
6
0
0
1
1
ADC5
ADC7
R/W
IPR
13
13
R
R
R
R
–
5
0
0
–
5
0
0
5
0
ADC4
ADC6
12
12
R
R
R
R
–
4
0
0
–
4
0
0
R
–
4
0
ADPS0
1
0
1
ADC3
ADC5
11
11
R
R
R
R
R
–
3
0
0
–
3
0
0
3
–
0
ADTS2
ADC2
ADC4
R/W
10
10
R
R
R
R
–
2
0
0
–
2
0
0
2
0
“ADC Conversion Result” on
ADTS1
ADC9
ADC1
ADC3
Division Factor
R/W
R
R
R
R
9
1
0
0
9
–
1
0
0
1
0
128
32
64
ADTS0
ADC8
ADC0
ADC2
R/W
R
R
R
R
8
0
0
0
8
–
0
0
0
0
0
ADCSRB
ADCH
ADCL
ADCH
ADCL
141
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