PIC12C509-04I/SM Microchip Technology, PIC12C509-04I/SM Datasheet - Page 25
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PIC12C509-04I/SM
Manufacturer Part Number
PIC12C509-04I/SM
Description
IC MCU OTP 1KX12 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC12C508A-04SM.pdf
(113 pages)
2.PIC12C508A-04SM.pdf
(4 pages)
3.PIC12C508-04P.pdf
(12 pages)
Specifications of PIC12C509-04I/SM
Core Size
8-Bit
Program Memory Size
1.5KB (1K x 12)
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Type
OTP
Ram Size
41 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Controller Family/series
PIC12
No. Of I/o's
6
Ram Memory Size
41Byte
Cpu Speed
4MHz
No. Of Timers
1
Digital Ic Case Style
SOIC
Package
8SOIJ
Device Core
PIC
Family Name
PIC12
Maximum Speed
4 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
5
Number Of Timers
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
6.0
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
• 8-bit software programmable prescaler
• Internal or external clock select
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two instruction cycles (Figure 6-2 and
Figure 6-3). The user can work around this by writing
an adjusted value to the TMR0 register.
FIGURE 6-1:
- Readable and writable
- Edge select for external clock
1999 Microchip Technology Inc.
GP2/T0CKI
TIMER0 MODULE AND
TMR0 REGISTER
Pin
T0SE
TIMER0 BLOCK DIAGRAM
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
F
OSC
2: The prescaler is shared with the Watchdog Timer (Figure 6-5).
/4
T0CS
0
1
(1)
PS2, PS1, PS0
Programmable
Prescaler
3
(2)
(1)
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
T0SE bit (OPTION<4>) determines the source edge.
Clearing the T0SE bit selects the rising edge.
Restrictions on the external clock input are discussed
in detail in Section 6.1.
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is
not readable or writable. When the prescaler is
assigned to the Timer0 module, prescale values of 1:2,
1:4,..., 1:256 are selectable. Section 6.2 details the
operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 6-1.
PSA
1
0
(1)
PSout
(2 T
Sync with
Internal
Clocks
CY
delay)
PIC12C5XX
PSout
Sync
TMR0 reg
Data bus
DS40139E-page 25
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