PIC16LF1933-I/ML Microchip Technology, PIC16LF1933-I/ML Datasheet - Page 134
![IC PIC MCU FLASH 4K 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LF1933-I/ML
Manufacturer Part Number
PIC16LF1933-I/ML
Description
IC PIC MCU FLASH 4K 28-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16LF1933-I/ML
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC16LF
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
32MHz
No. Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F193X/LF193X
TABLE 12-1:
TABLE 12-2:
DS41364D-page 134
CONFIG1
CONFIG2
Legend:
Note
ADCON0
ADCON1
ANSELA
APFCON
CM1CON0
CM2CON0
CM1CON1
CM2CON1
CPSCON0
CPSCON1
DACCON0
LATA
LCDCON
LCDSE0
LCDSE1
OPTION_REG
PORTA
SRCON0
SSPxCON1
TRISA
Legend:
Note 1:
Name
Name
1:
2:
— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.
PIC16F193X only.
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
PIC16F193X only.
The Capacitive Sensing Reference Mode (CPSRM) bit is not available for the PIC16F/LF1934/1936 devices.
Bits
13:8
13:8
7:0
7:0
WPUEN
CPSON
DACEN
LCDEN
TRISA7
C1NTP
C2NTP
SRLEN
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
WCOL
SUMMARY OF CONFIGURATION WORD WITH PORTA
ADFM
C1ON
C2ON
LATA7
SE15
Bit 7
SE7
RA7
—
—
—
—
Bit -/7
CP
—
—
—
CCP3SEL
CPSRM
DACLPS
SSPxOV
INTEDG
C1INTN
C2INTN
TRISA6
C1OUT
C2OUT
SLPEN
LATA6
SE14
Bit 6
MCLRE
SE6
RA6
Bit -/6
—
—
—
—
—
(2)
SRCLK<2:0>
ADCS<2:0>
TMR0CS
T1GSEL
SSPxEN
DACOE
TRISA5
ANSA5
WERR
LATA5
C1OE
C2OE
SE13
Bit 5
Bit 13/5
FCMEN
PWRTE
SE5
RA5
—
—
LVP
C1PCH<1:0>
C2PCH<1:0>
VCAPEN<1:0>
CHS<4:0>
Preliminary
TMR0SE
P2BSEL
TRISA4
ANSA4
C1POL
C2POL
LATA4
SE12
Bit 4
CKP
SE4
RA4
Bit 12/4
DEBUG
—
—
---
—
IESO
(1)
WDTE<1:0>
SRNQSEL C2OUTSEL
SRQEN
TRISA3
ANSA3
CLKOUTEN
LATA3
SE11
Bit 3
PSA
RA3
SE3
CPSRNG<1:0>
Bit 11/3
—
—
—
—
—
DACPSS<1:0>
—
—
CS<1:0>
SRNQEN
ADNREF
TRISA2
ANSA2
LATA2
C1SP
C2SP
SE10
Bit 2
SE2
RA2
Bit 10/2
—
—
CPSCH<3:0>
BORV
SSPxM<3:0>
—
BOREN<1:0>
GO/DONE
CPSOUT
PS<2:0>
TRISA1
ANSA1
SSSEL
C1HYS
C2HYS
LATA1
FOSC<2:0>
SRPS
Bit 1
SE1
SE9
RA1
STVREN
2009 Microchip Technology Inc.
ADPREF<1:0>
---
Bit 9/1
C1NCH<1:0>
C2NCH<1:0>
LMUX<1:0>
WRT<1:0>
CCP2SEL
DACNSS
C1SYNC
C2SYNC
TRISA0
ANSA0
T0XCS
ADON
LATA0
SRPR
Bit 0
RA0
SE0
SE8
PLLEN
Bit 8/0
CPD
Register
on Page
Register
on Page
161
162
133
130
180
180
181
181
323
324
172
132
329
333
333
191
132
185
285
132
64
66
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