PIC18F24J10-I/SP Microchip Technology, PIC18F24J10-I/SP Datasheet - Page 112
![IC PIC MCU FLASH 8KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F24J10-I/SP
Manufacturer Part Number
PIC18F24J10-I/SP
Description
IC PIC MCU FLASH 8KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18F44J10-IPT.pdf
(358 pages)
Specifications of PIC18F24J10-I/SP
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28P
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18F44J10-IPT PDF datasheet #6
- Current page: 112 of 358
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
FIGURE 9-4:
FIGURE 9-5:
TABLE 9-13:
DS39682C-page 110
PORTD
LATD
TRISD
PORTE
LATE
TRISE
INTCON
PIR1
PIE1
IPR1
ADCON1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1:
Name
PORTD<7:0>
PORTD<7:0>
(1)
(1)
(1)
(1)
(1)
(1)
These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.
PSPIF
PSPIF
PORTD Data Latch Register (Read and Write to Data Latch)
PORTD Data Direction Control Register
GIE/GIEH PEIE/GIEL
OBF
PSPIE
PSPIP
PSPIF
OBF
CS
WR
RD
IBF
CS
WR
RD
IBF
Bit 7
RD7
IBF
—
—
—
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
(1)
(1)
(1)
PARALLEL SLAVE PORT WRITE WAVEFORMS
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q1
ADIF
ADIE
ADIP
Bit 6
RD6
OBF
—
—
—
Q2
Q2
TMR0IE
VCFG1
IBOV
RCIF
RCIE
RCIP
Bit 5
RD5
Q3
Q3
—
—
Q4
Q4
PSPMODE
VCFG0
INT0IE
Preliminary
TXIE
TXIP
Bit 4
TXIF
RD4
—
—
Q1
Q1
SSP1IF
SSP1IE
SSP1IP
PCFG3
Q2
Q2
RBIE
Bit 3
RD3
—
—
—
Q3
Q3
PORTE Data Latch Register
(Read and Write to Data Latch)
TMR0IF
CCP1IE
CCP1IP
TRISE2
CCP1IF
PCFG2
Bit 2
RD2
RE2
Q4
Q4
TMR2IF
TMR2IE
TMR2IP
TRISE1
PCFG1
INT0IF
Q1
Q1
Bit 1
© 2007 Microchip Technology Inc.
RD1
RE1
Q2
Q2
TMR1IF
TMR1IE
TMR1IP
TRISE0
PCFG0
RBIF
Bit 0
RD0
RE0
Q3
Q3
on page
Values
Reset
Q4
Q4
46
46
46
46
46
46
43
45
45
45
44
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