PIC18F24K20-I/SP Microchip Technology, PIC18F24K20-I/SP Datasheet - Page 221
![IC PIC MCU FLASH 8KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F24K20-I/SP
Manufacturer Part Number
PIC18F24K20-I/SP
Description
IC PIC MCU FLASH 8KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(12 pages)
3.PIC18F25K20T-ISS.pdf
(14 pages)
4.PIC18F25K20T-ISS.pdf
(456 pages)
5.PIC18F26K20-ISO.pdf
(430 pages)
Specifications of PIC18F24K20-I/SP
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
CCP/ECCP/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC18F25K20T-ISS PDF datasheet
- PIC18F25K20T-ISS PDF datasheet #2
- PIC18F25K20T-ISS PDF datasheet #3
- PIC18F25K20T-ISS PDF datasheet #4
- PIC18F26K20-ISO PDF datasheet #5
- Current page: 221 of 456
- Download datasheet (4Mb)
17.4.7
In I
reload value is placed in the SSPADD register
(Figure 17-17). When a write occurs to SSPBUF, the
Baud Rate Generator will automatically begin counting.
The BRG counts down to ‘0’ and stops until another
reload has taken place. The BRG count is decre-
mented twice per instruction cycle (T
Q4 clocks. In I
automatically. One half of the SCL period is equal to
[(SSPADD+1) 2]/F
(F
FIGURE 17-17:
TABLE 17-3:
2010 Microchip Technology Inc.
Note 1:
CY
2
C Master mode, the Baud Rate Generator (BRG)
/F
SCL
) -1.
64 MHz
64 MHz
64 MHz
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
BAUD RATE
F
OSC
2
C Master mode, the BRG is reloaded
2
C interface does not conform to the 400 kHz I
I
2
C™ CLOCK RATE W/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
OSC
SSPM<3:0>
. Therefore SSPADD =
SCL
CY
) on the Q2 and
16 MHz
16 MHz
16 MHz
10 MHz
10 MHz
10 MHz
SSPM<3:0>
4 MHz
4 MHz
4 MHz
1 MHz
F
CY
Reload
Control
CLKOUT
Reload
Once
transmission of the last data bit is followed by ACK), the
internal clock will automatically stop counting and the
SCL pin will remain in its last state.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
The minimum SSPADD value for baud rate generation
is 0x03.
2
PIC18F2XK20/4XK20
BRG Down Counter
C specification (which applies to rates greater than
SSPADD<7:0>
BRG Value
the
0Ch
3Fh
1Fh
27h
32h
18h
63h
09h
27h
09h
given
operation
F
OSC
(2 Rollovers of BRG)
/2
is
400 kHz
400 kHz
400 kHz
313.7 kHz
312.5 kHz
DS41303G-page 221
250 kHz
100 kHz
308 kHz
100 kHz
100 kHz
F
complete
SCL
(1)
(1)
(1)
(i.e.,
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