ATTINY2313-20PU Atmel, ATTINY2313-20PU Datasheet - Page 156

• Manufacturer Part Number: ATTINY2313-20PU
• Description: IC MCU AVR 2K FLASH 20DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313-20PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Package: 20PDIP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 18
• Interface Type: SPI/USART/USI
• Number Of Timers: 2
• Processor Series: ATTINY2x
• Core: AVR8
• Data Ram Size: 128 B
• Maximum Clock Frequency: 20 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATtiny
• Device Core Size: 8b
• Frequency (max): 20MHz
• Total Internal Ram Size: 128Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

EEPROM Write
Prevents Writing to
SPMCSR
Reading the Fuse and
Lock Bits from
Software
156
ATtiny2313
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the RFLB and SELFPRGEN bits in SPMCSR. When an LPM
instruction is executed within three CPU cycles after the RFLB and SELFPRGEN bits are set in
SPMCSR, the value of the Lock bits will be loaded in the destination register. The RFLB and
SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM instruc-
tion is executed within three CPU cycles or no SPM instruction is executed within four CPU
cycles. When RFLB and SELFPRGEN are cleared, LPM will work as described in the Instruction
set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the RFLB and
SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles after
the RFLB and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB)
will be loaded in the destination register as shown below. Refer to
detailed description and mapping of the Fuse Low byte.
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-
tion is executed within three cycles after the RFLB and SELFPRGEN bits are set in the
SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as
shown below. Refer to
High byte.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
Bit
Rd
Bit
Rd
Bit
Rd
FLB7
FHB7
7
7
7
–
FHB6
FLB6
Table 67 on page 159
6
6
6
–
FHB5
FLB5
5
–
5
5
FHB4
FLB4
4
–
4
4
for detailed description and mapping of the Fuse
FHB3
FLB3
3
–
3
3
FLB2
FHB2
2
–
2
2
FHB1
FLB1
LB2
1
1
1
Table 68 on page 160
FHB0
FLB0
LB1
0
0
0
2543L–AVR–08/10
for a