ATTINY2313V-10PU Atmel, ATTINY2313V-10PU Datasheet - Page 42
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ATTINY2313V-10PU
Manufacturer Part Number
ATTINY2313V-10PU
Description
IC MCU AVR 2K FLASH 20DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheets
1.ATTINY2313-20MU.pdf
(226 pages)
2.ATTINY2313V-10MU.pdf
(15 pages)
3.ATTINY2313V-10SU.pdf
(20 pages)
Specifications of ATTINY2313V-10PU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI/UART/USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
18
Number Of Timers
2
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Package
20PDIP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
10 MHz
Data Rom Size
128 B
Height
4.95 mm
Length
26.92 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Width
7.11 mm
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY2313V-10PU
Manufacturer:
ATMEL
Quantity:
3 000
Part Number:
ATTINY2313V-10PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Watchdog Timer
Control Register -
WDTCSR
42
ATtiny2313
• Bit 7 - WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-
ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in
SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is
enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt
Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in
the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE
and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is use-
ful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and
System Reset Mode, WDIE must be set after each interrupt. This should however not be done
within the interrupt service routine itself, as this might compromise the safety-function of the
Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a Sys-
tem Reset will be applied.
Table 19. Watchdog Timer Configuration
Note:
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,
and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is
set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-
ditions causing failure, and a safe start-up after the failure.
• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-
ning. The different prescaling values and their corresponding time-out periods are shown in
Table 20 on page
Bit
Read/Write
Initial Value
WDTON
1
1
1
1
0
1. WDTON Fuse set to “0“ means programmed and “1” means unprogrammed.
(1)
WDIF
R/W
7
0
WDE
43.
0
0
1
1
x
WDIE
R/W
6
0
WDIE
WDP3
0
1
0
1
x
R/W
5
0
WDCE
Mode
Stopped
Interrupt Mode
System Reset Mode
Interrupt and System
Reset Mode
System Reset Mode
R/W
0
4
WDE
R/W
3
X
WDP2
R/W
2
0
WDP1
R/W
Action on Time-out
None
Interrupt
Reset
Interrupt, then go to
System Reset Mode
Reset
1
0
WDP0
R/W
0
0
WDTCSR
2543L–AVR–08/10