PIC16LF1934-I/ML Microchip Technology, PIC16LF1934-I/ML Datasheet - Page 342
![IC PIC MCU FLASH 256KX7 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC16LF1934-I/ML
Manufacturer Part Number
PIC16LF1934-I/ML
Description
IC PIC MCU FLASH 256KX7 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16LF1933-ISS.pdf
(508 pages)
2.PIC16LF1933-ISS.pdf
(46 pages)
3.PIC16LF1934-IML.pdf
(418 pages)
Specifications of PIC16LF1934-I/ML
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART/MI2C/SPI
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
36
Number Of Timers
5
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
14-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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PIC16F193X/LF193X
TABLE 26-3:
DS41364A-page 340
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
ADDFSR
MOVIW
MOVWI
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
Mnemonic,
Operands
2:
is executed as a NOP.
If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
k
–
k
–
k
k
k
–
–
–
–
–
–
f
n, k
mm n
n mm
k[n]
mm n
n mm
k[n]
PIC16F193X/LF193X ENHANCED INSTRUCTION SET (CONTINUED)
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
Clear Watchdog Timer
No Operation
Load OPTION_REG register with W
Software device Reset
Go into Standby mode
Load TRIS register with W
Add Literal to FSRn
Move INDFn to W, with pre/post inc/dec
Move INDFn to W, with pre/post inc/dec
Move INDFn to W, Indexed Indirect.
Move W to INDFn, with pre/post inc/dec
Move W to INDFn, with pre/post inc/dec
Move W to INDFn, Indexed Indirect.
Description
C-COMPILER OPTIMIZED
INHERENT OPERATIONS
CONTROL OPERATIONS
Preliminary
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
Cycles
11
00
10
00
10
00
11
00
00
00
00
00
00
00
MSb
11
00
00
11
00
00
11
14-Bit Opcode
001k
0000
0kkk
0000
1kkk
0000
0100
0000
0000
0000
0000
0000
0000
0000
0001
0000
0000
1111
0000
0000
1111
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
0110
0000
0110
0000
0110
0110
0nkk
1nkk
0nkk
0001
0001
0001
0001
© 2008 Microchip Technology Inc.
kkkk
1011
kkkk
1010
kkkk
1001
kkkk
1000
0100
0000
0010
0001
0011
01kk
0nmm
kkkk
kkkk
kkkk
0mmn
1mmn
1nmm
LSb
TO, PD
TO, PD
Z
Z
Z
Affected
Status
2
2
2
2
2
2
Notes
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