PIC16F627-04/P Microchip Technology, PIC16F627-04/P Datasheet
PIC16F627-04/P
Specifications of PIC16F627-04/P
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PIC16F627-04/P Summary of contents
Page 1
... TRISB register latch. FIGURE 5-8: BLOCK DIAGRAM OF RB0/INT PIN Data Bus PORTB CK Data Latch TRISB CK TRIS Latch RD TRISB RD PORTB INT Input © 2005 Microchip Technology Inc. PIC16F62X RBPU TTL Input Buffer Weak P Pull-up RB0/INT pin ...
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... RD PORTB USART Receive Input Note 1: Port/Peripheral select signal selects between port data and peripheral output. 2: Peripheral OE (output enable) is only active if peripheral select is active. DS80073G-page 2 RBPU TTL Input Buffer Schmitt Trigger V DD Weak Pull- RB1/RX/DT pin PORTB © 2005 Microchip Technology Inc. ...
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... WR PORTB CK Data Latch D WR TRISB CK TRIS Latch RD TRISB (2) Peripheral OE RD PORTB USART Slave Clock In Note 1: Port/Peripheral select signal selects between port data and peripheral output. 2: Peripheral OE (output enable) is only active if peripheral select is active. © 2005 Microchip Technology Inc. RBPU Schmitt Trigger ...
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... Port/Peripheral Select PWM/Compare Output Data Bus D WR PORTB CK Data Latch D WR TRISB TRIS Latch RD TRISB RD PORTB CCP Input Note 1: Peripheral select is defined by CCP1M3:CCP1M0 (CCP1CON<3:0>). DS80073G-page 4 RBPU Schmitt Trigger Weak Pull- RB3/CCP1 pin Vss TTL Input Buffer PORTB © 2005 Microchip Technology Inc. ...
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... FIGURE 5-12: BLOCK DIAGRAM OF RB4/PGM PIN Data Bus WR PORTB Data Latch WR TRISB RD TRISB LVP RD PORTB PGM Input Note 1: The Low Voltage Programming disables the interrupt-on-change and the weak pull-ups on RB4. © 2005 Microchip Technology Inc. RBPU TRIS Latch Schmitt Trigger Set RBIF From other RB< ...
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... PIC16F62X FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN Data Bus PORTB CK Data Latch TRISB CK TRIS Latch RD TRISB RD PORTB Set RBIF From other RB<7:4> pins DS80073G-page 6 RBPU TTL Input Buffer Port EN Q3 © 2005 Microchip Technology Inc Weak DD P Pull-up RB5 pin V SS ...
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... FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI PIN Data Bus D WR PORTB CK Data Latch D WR TRISB CK TRIS Latch RD TRISB T1OSCEN RD PORTB TMR1 Clock From RB7 Serial Programming Clock © 2005 Microchip Technology Inc. RBPU Schmitt Trigger TMR1 Oscillator Q Set RBIF From other Q RB<7:4> pins PIC16F62X V ...
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... WR PORTB WR TRISB TRIS Latch RD TRISB T10SCEN RD PORTB Serial Programming Input Set RBIF DS80073G-page Weak Pull- RB6 T1OSCEN Data Latch Schmitt Trigger From other Q D RB<7:4> pins EN TMR1 Oscillator RB7/T1OSI pin Vss TTL Input Buffer Q1 RD Port Q3 © 2005 Microchip Technology Inc. ...
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... CCPR1<0> bit. This gives the appearance of an inverted CCP response to the third and subsequent compare match events. © 2005 Microchip Technology Inc. The apparent inverted response will persist until the CCP1CON<3> bit is cleared (exiting Compare mode). Interrupts always occur correctly on the match condition ...
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... Other (non power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal operation. DS80073G-page 10 Registers Registers Bit 5 Bit 4 Bit 3 Bit 2 T1CKPS0 T1OSCEN T1SYNC CREN ADDEN FERR Value on all Value on Bit 1 Bit 0 other POR Reset (1) Resets TMR1CS TMR1ON --00 0000 --uu uuuu OERR RX9D 0000 -00x 0000 -00x © 2005 Microchip Technology Inc. ...
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... Module: I/O Ports (RA5/MCLR/V Figure 5-5, “Block Diagram of the RA5/MCLR/V Pin”, is incorrect. The following diagram should be used instead. FIGURE 5-5: BLOCK DIAGRAM OF THE RA5/MCLR/VPP PIN MCLR Circuit Program Mode Data Bus RD Port © 2005 Microchip Technology Inc MCLRE (1) MCLR Filter HV Detect Q D ...
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... TRIS<5> always reads '0' ; Select BANK 0 ; Wait 10us for comparator output to become valid ; See Table 17-1 Parameter 301 ; Read CMCON to end change condition ; Clear pending interrupts ; Select BANK 1 ; Enable Comparator Interrupts ; Select BANK 0 ; Enable Peripheral Interrupts ; Global Interrupt Enable © 2005 Microchip Technology Inc. ...
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... Is the value written (in W Reg) and ; read (in EEDATA) the same? ; SUBWF EEDATA the EEDATA has fresh data BTFSS STATUS the Zero flag set? GOTO WRITE_ERR ; NO, Write Error ; YES, Good Write ; continue program © 2005 Microchip Technology Inc. PIC16F62X DS80073G-page 13 ...
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... R = Readable bit -n = Value at POR DS80073G-page 14 R/W-0 R/W-0 R/W-0 T1CKPS1 T1CKPS0 T1OSCEN (1) /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit Bit is unknown © 2005 Microchip Technology Inc. ...
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... Item 2, Tables 17.1 and 17.2, were updated with minor changes. Item 6 was added. Rev E Document (2/02) Under Clarifications/Corrections to the Data Sheet, added Module 3: I/O Ports (RA5/MCLR/V Rev G Document (05/19/05) Under Clarifications/Corrections to the Data Sheet, Added Module 6: Timer1 Module. © 2005 Microchip Technology Inc PIC16F62X DS80073G-page 15 ...
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... PIC16F62X NOTES: DS80073G-page 16 © 2005 Microchip Technology Inc. ...
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... PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Fax: 65-6334-8850 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Taiwan - Hsinchu Tel: 886-3-572-9526 Fax: 886-3-572-6459 © 2005 Microchip Technology Inc. EUROPE Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Ballerup Tel: 45-4450-2828 Fax: 45-4485-2829 France - Massy Tel: 33-1-69-53-63-20 ...