PIC18LF13K50-I/P Microchip Technology, PIC18LF13K50-I/P Datasheet - Page 25
![IC PIC MCU FLASH 4KX16 20-PDIP](/photos/12/13/121303/150-20-dip_sml.jpg)
PIC18LF13K50-I/P
Manufacturer Part Number
PIC18LF13K50-I/P
Description
IC PIC MCU FLASH 4KX16 20-PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(40 pages)
3.PIC18F13K50-ISS.pdf
(10 pages)
4.PIC18F13K50-ISS.pdf
(2 pages)
5.PIC18F13K50-ISO.pdf
(414 pages)
Specifications of PIC18LF13K50-I/P
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
15
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
48MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
5.3
A Configuration address may be read and output on
PGD via the 4-bit command, ‘1001’. Configuration data
is read and written in a byte-wise fashion, so it is not
necessary to merge two bytes into a word prior to a
compare. The result may then be immediately
compared to the appropriate Configuration data in the
programmer’s memory for verification. Refer to
Section 5.1 “Read Program Flash, ID Locations and
Configuration Bits” for implementation details of
reading Configuration data.
5.4
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair EEADRH:EEADR) and a
data latch (EEDATA). Data EEPROM is read by
loading EEADRH: EEADR with the desired memory
location and initiating a memory read by appropriately
configuring the EECON1 register. The data will be
loaded into EEDATA, where it may be serially output on
PGD via the 4-bit command, ‘0010’ (Shift Out Data
Holding register). A delay of P6 must be introduced
after the falling edge of the 8th PGC of the operand to
allow PGD to transition from an input to an output.
During this time, PGC must be held low, as shown in
Figure 5-4.
The command sequence to read a single byte of data
is shown in Table 5-2.
TABLE 5-2:
2010 Microchip Technology Inc.
Step 1: Direct access to data EEPROM.
Step 2: Set the data EEPROM Address Pointer.
Step 3: Initiate a memory read.
Step 4: Load data into the Serial Data Holding register.
Note 1:
Command
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0010
4-bit
Verify Configuration Bits
Read Data EEPROM Memory
The <LSB> is undefined. The <MSB> is the data.
READ DATA EEPROM MEMORY
<MSB><LSB>
Data Payload
OE <AddrH>
0E <Addr>
9C A6
6E AA
9E A6
6E A9
6E F5
80 A6
50 A8
00 00
PIC18F1XK50/PIC18LF1XK50
BCF EECON1, EEPGD
BCF EECON1, CFGS
MOVLW <Addr>
MOVWF EEADR
MOVLW <AddrH>
MOVWF EEADRH
BSF EECON1, RD
MOVF EEDATA, W, 0
MOVWF TABLAT
NOP
Shift Out Data
Advance Information
(1)
FIGURE 5-3:
Core Instruction
No
Move to TABLAT
Shift Out Data
READ DATA EEPROM
FLOW
Address
done?
Read
Byte
Start
Done
Set
Yes
DS41342E-page 25