PIC12C672-10I/P Microchip Technology, PIC12C672-10I/P Datasheet - Page 227
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PIC12C672-10I/P
Manufacturer Part Number
PIC12C672-10I/P
Description
IC MCU OTP 2KX14 A/D 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C672-10I/P
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Core Processor
PIC
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Controller Family/series
PIC12
No. Of I/o's
6
Ram Memory Size
128Byte
Cpu Speed
10MHz
No. Of Timers
1
Digital Ic Case Style
DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Eeprom Size
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- Current page: 227 of 688
- Download datasheet (3Mb)
Microwire is a trademark of National Semiconductor.
1997 Microchip Technology Inc.
The SSP consists of a transmit/receive Shift Register (SSPSR) and a buffer register (SSPBUF).
The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that
was written to the SSPSR, until the received data is ready. Once the 8-bits of data have been
received, that byte is moved to the SSPBUF register. Then the buffer full detect bit, BF
(SSPSTAT<0>), and interrupt flag bit, SSPIF, are set. This double buffering of the received data
(SSPBUF) allows the next byte to start reception before reading the data that was just received.
Any write to the SSPBUF register during transmission/reception of data will be ignored, and the
write collision detect bit, WCOL (SSPCON<7>), will be set. User software must clear the WCOL
bit so that it can be determined if the following write(s) to the SSPBUF register completed suc-
cessfully. When the application software is expecting to receive valid data, the SSPBUF should
be read before the next byte of data to transfer is written to the SSPBUF. Buffer full bit, BF
(SSPSTAT<0>), indicates when SSPBUF has been loaded with the received data (transmission
is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally the SSP Interrupt is used to determine when the transmis-
sion/reception has completed. The SSPBUF must be read and/or written. If the interrupt method
is not going to be used, then software polling can be done to ensure that a write collision does
not occur.
shaded instruction is only required if the received data is meaningful (some SPI applications are
transmit only).
Example 15-1:
The SSPSR is not directly readable or writable, and can only be accessed from addressing the
SSPBUF register. Additionally, the SSP status register (SSPSTAT) indicates the various status
conditions.
LOOP BTFSS SSPSTAT, BF
BCF
BSF
GOTO
BCF
MOVF
MOVWF RXDATA
MOVF
MOVWF SSPBUF
Example 15-1
STATUS, RP1
STATUS, RP0
LOOP
STATUS, RP0
SSPBUF, W
TXDATA, W
Loading the SSPBUF (SSPSR) Register
shows the loading of the SSPBUF (SSPSR) for data transmission. The
;Specify Bank1
;
;Has data been received (transmit complete)?
;No
;Specify Bank0
;W reg = contents of SSPBUF
;Save in user RAM, if data is meaningful
;W reg = contents of TXDATA
;New data to xmit
Section 15. SSP
DS31015A-page 15-7
15
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