PIC12CE673-04/P Microchip Technology, PIC12CE673-04/P Datasheet - Page 296
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC12CE673-04/P
Manufacturer Part Number
PIC12CE673-04/P
Description
IC MCU OTP 1KX14 A/D&EE 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(3 pages)
4.PIC12CE673-10P.pdf
(14 pages)
5.PIC12CE673-10P.pdf
(12 pages)
Specifications of PIC12CE673-04/P
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Type
OTP
Eeprom Size
16 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-DIP (0.300", 7.62mm)
Controller Family/series
PIC12
No. Of I/o's
6
Eeprom Memory Size
16Byte
Ram Memory Size
128Byte
Cpu Speed
4MHz
No. Of Timers
1
Processor Series
PIC12C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
5
Number Of Timers
8
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
0 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12CE673-04/P
Manufacturer:
Microchip
Quantity:
486
- PIC16F688T-ISL PDF datasheet
- PIC12CE673-10P PDF datasheet #2
- PIC12CE673-10P PDF datasheet #3
- PIC12CE673-10P PDF datasheet #4
- PIC12CE673-10P PDF datasheet #5
- Current page: 296 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.4.1
DS31017A-page 17-20
Slave Mode
In slave mode, the SCL and SDA pins must be configured as inputs. The SSP module will over-
ride the input state with the output data when required (slave-transmitter).
When an address is matched or the data transfer after an address match is received, the hard-
ware automatically will generate the acknowledge (ACK) pulse, and then load the SSPBUF reg-
ister with the received value currently in the SSPSR register.
There are certain conditions that will cause the SSP module not to give this ACK pulse. These
are if either (or both):
a)
b)
If the BF bit is set, the SSPSR register value is not loaded into the SSPBUF, but the SSPIF and
SSPOV bits are set.
the status of the BF and SSPOV bits. The shaded cells show the condition where user software
did not properly clear the overflow condition. The BF flag bit is cleared by reading the SSPBUF
register while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and low time for proper operation. The high and
low times of the I
parameters 100
The buffer full bit, BF (SSPSTAT<0>), was set before the transfer was received.
The overflow bit, SSPOV (SSPCON1<6>), was set before the transfer was received.
2
and
C specification as well as the requirement of the SSP module is shown in timing
Table 17-2
101
of the
Preliminary
shows what happens when a data transfer byte is received, given
“Electrical Specifications”
section.
1997 Microchip Technology Inc.
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