PIC16F72-I/ML Microchip Technology, PIC16F72-I/ML Datasheet - Page 78
![IC PIC MCU FLASH 2KX14 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16F72-I/ML
Manufacturer Part Number
PIC16F72-I/ML
Description
IC PIC MCU FLASH 2KX14 28-QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F72-ISO.pdf
(136 pages)
5.PIC16F72-ISO.pdf
(6 pages)
6.PIC16F72-ISO.pdf
(136 pages)
Specifications of PIC16F72-I/ML
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC16F
No. Of I/o's
22
Ram Memory Size
128Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
PIC16F72-I/MLR
PIC16F72-I/MLR
PIC16F72-I/MLR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
PIC16F72
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Description:
BTFSC
Syntax:
Operands:
Operation:
Status Affected:
Description:
CALL
Syntax:
Operands:
Operation:
Status Affected:
Description:
DS39597B-page 76
Bit Test, Skip if Clear
[ label ] BTFSC f,b
0 ≤ f ≤ 127
0 ≤ b ≤ 7
skip if (f<b>) = 0
None
If bit ‘b’ in register ‘f’ = ‘1’, the next
instruction is executed.
If bit ‘b’ in register ‘f’ = ‘0’, the next
instruction is discarded, and a NOP
is executed instead, making this a
2 T
Bit Test f, Skip if Set
[ label ] BTFSS f,b
0 ≤ f ≤ 127
0 ≤ b < 7
skip if (f<b>) = 1
None
If bit ‘b’ in register ‘f’ = ‘0’, the next
instruction is executed.
If bit ‘b’ = ‘1’, then the next instruc-
tion is discarded and a NOP is exe-
cuted instead, making this a 2 T
instruction.
Call Subroutine
[ label ] CALL k
0 ≤ k ≤ 2047
(PC) + 1 → TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
None
Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven-bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALL is
a two-cycle instruction.
CY
instruction.
CY
CLRF
Syntax:
Operands:
Operation:
Status Affected:
Description:
CLRW
Syntax:
Operands:
Operation:
Status Affected:
Description:
CLRWDT
Syntax:
Operands:
Operation:
Status Affected:
Description:
Clear W
[ label ] CLRW
None
00h → (W)
1 → Z
Z
W register is cleared. Zero bit (Z)
is set.
Clear Watchdog Timer
[ label ] CLRWDT
None
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
TO, PD
CLRWDT instruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits
TO and PD are set.
Clear f
[ label ] CLRF
0 ≤ f ≤ 127
00h → (f)
1 → Z
Z
The contents of register ‘f’ are
cleared and the Z bit is set.
2002 Microchip Technology Inc.
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