ATTINY84-20PU Atmel, ATTINY84-20PU Datasheet - Page 131
![IC MCU AVR 8K FLASH 20MHZ 14-DIP](/photos/7/39/73953/313-14-dip_sml.jpg)
ATTINY84-20PU
Manufacturer Part Number
ATTINY84-20PU
Description
IC MCU AVR 8K FLASH 20MHZ 14-DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY84-20PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
12
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-DIP (0.300", 7.62mm)
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
AVR Tiny
No. Of I/o's
12
Eeprom Memory Size
512Byte
Ram Memory Size
512Byte
Cpu Speed
20MHz
No. Of Timers
2
Rohs Compliant
Yes
Package
14PDIP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
20 MHz
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY84-20PU
Manufacturer:
XILINX
Quantity:
25
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15.2.2
15.2.3
8006K–AVR–10/10
ADCSRB – ADC Control and Status Register B
DIDR0 – Digital Input Disable Register 0
between the Analog Comparator and the input capture function exists. To make the comparator
trigger the Timer/Counter1 Input Capture inter-rupt, the ICIE1 bit in the Timer Interrupt Mask
Register (TIMSK1) must be set.
• Bits 1:0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt. The
different settings are shown in
Table 15-2.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the
bits are changed.
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the
ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written
logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed
description of this bit, see
• Bits 2:1 – ADC2D, ADC1D: ADC 2/1 Digital input buffer disable
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corre-
sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is
applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-
ten logic one to reduce power consumption in the digital input buffer.
Bit
0x03 (0x23)
Read/Write
Initial Value
Bit
0x01 (0x21)
Read/Write
Initial Value
ACIS1
0
0
1
1
ACIS1/ACIS0 Settings
ADC7D
R/W
R/W
BIN
7
0
7
0
ACIS0
0
1
0
1
ADC6D
ACME
R/W
R/W
“Analog Comparator Multiplexed Input” on page
6
0
6
0
Interrupt Mode
Comparator Interrupt on Output Toggle.
Reserved
Comparator Interrupt on Falling Output Edge.
Comparator Interrupt on Rising Output Edge.
Table
ADC5D
R/W
5
0
R
5
–
0
15-2.
ADC4D
ADLAR
R/W
R/W
4
0
4
0
ADC3D
R/W
3
0
R
3
–
0
ADC2D
ADTS2
R/W
R/W
2
0
2
0
ATtiny24/44/84
ADC1D
ADTS1
R/W
R/W
1
0
1
0
129.
ADC0D
ADTS0
R/W
R/W
0
0
0
0
ADCSRB
DIDR0
131
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