PIC16LF818-I/SO Microchip Technology, PIC16LF818-I/SO Datasheet - Page 3
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PIC16LF818-I/SO
Manufacturer Part Number
PIC16LF818-I/SO
Description
IC MCU FLASH 1KX14 EEPROM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(176 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F818-ISO.pdf
(8 pages)
5.PIC16F818-ISO.pdf
(8 pages)
Specifications of PIC16LF818-I/SO
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Controller Family/series
PIC16LF
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
128Byte
Cpu Speed
20MHz
No. Of Timers
3
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C, SPI, SSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
1 x 16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF818-I/SO
Manufacturer:
MICROCHIP
Quantity:
1 001
Part Number:
PIC16LF818-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
2. Module: Internal RC Oscillator
3. Module: PORTB Pull-ups
© 2005 Microchip Technology Inc.
When any one of the seven INTOSC frequencies
is enabled by the following conditions, it is possible
for the oscillator to overshoot the selected
frequency.:
1. A clock switch from INTRC (31 kHz) to an
2. Exit from Sleep mode with the IRCF bits
If the selected frequency is 8 MHz, then the
Voltage versus Frequency specification of the
device may be violated.
Work around
When it is required for the application to run at
8 MHz, it is recommended that the application
does not start executing code at 8 MHz until the
60ms firmware delay (see issue 1) has completed.
During the 60 ms settling period, the application
can execute code up to 4 MHz. Upon completion
of the 60 ms firmware delay, the 8 MHz can be
selected via the IRCF bits.
Date Codes that pertain to this issue:
All date codes.
When RBPU = 0 (OPTION register), the PORTB
weak pull-ups will not be disabled by the input
functions of the SSP and/or CCP (Capture mode)
module as indicated by the RB1:RB5 I/O block
diagrams in Section 5.0 “I/O Ports”.
Work around
1. If the SSP and/or CCP (Capture mode) module
OR
2. If the SSP and/or CCP (Capture mode) module
Date Codes that pertain to this issue:
All date codes.
INTOSC (125 kHz-8 MHz) frequency via the
IRCF bits (OSCCON register).
already configured for an INTOSC frequency.
is enabled, do not enable the PORTB weak
pull-ups and use external pull-up resistors.
and PORTB pull-ups are enabled, then evalu-
ate the functionality of the SSP (I
or CCP (Capture mode) module to ensure
proper operation within your application.
2
C™/SPI™)
4. Module: PORTB
5. Module: PORTB Interrupts
A delay of 1 T
modifies the contents of PORTB simultaneously
occurs when any of the following modules (if
enabled) executes an operation that effects the
signals on their respective PORTB I/O pins.
CCP Module:
PWM Mode (CCP1CON<3:0> = 11xx)
When CCP1CON<5:4> bits = 10, the PWM output
signal will be delayed by 1 T
instruction to modify the contents of PORTB is
executed.
SSP Module:
SPI Slave Modes (SSPCON<3:0> = 0100 and 0101)
Clock signal is derived from an external source.
Transmission of data (SDO pin) will be delayed by
1 T
of PORTB is executed. Reception of data is not
affected.
Work around
None
Date Codes that pertain to this issue:
All date codes.
When the PORTB interrupt-on-change feature and
a PORTB peripheral are enabled simultaneously,
the PORTB peripheral input signal’s rising and
falling edges will trigger an interrupt-on-change
event. This is due to the interrupt-on-change
feature not being disabled on the respective pin for
that peripheral when it is enabled.
The affected pins and peripheral signals on
PORTB are RB4: SCK and SCL, RB5: SS and
RB6: T1CKI. The functionality of T1OSI (RB7) and
T1OSO (RB6) is not affected by this issue.
Work around
None.
OSC
when an instruction to modify the contents
PIC16F818/819
OSC
will occur if an instruction that
DS80212C-page 3
OSC
when an