PIC24FJ16GA002-I/SO Microchip Technology, PIC24FJ16GA002-I/SO Datasheet - Page 103
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PIC24FJ16GA002-I/SO
Manufacturer Part Number
PIC24FJ16GA002-I/SO
Description
IC PIC MCU FLASH 16K 28-SOIC
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ16GA002-ISS.pdf
(268 pages)
3.PIC24FJ16GA002-ISS.pdf
(22 pages)
4.PIC24FJ64GA004-EPT.pdf
(262 pages)
Specifications of PIC24FJ16GA002-I/SO
Core Size
16-Bit
Program Memory Size
16KB (5.5K x 24)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
PIC24
No. Of I/o's
21
Ram Memory Size
4KB
Cpu Speed
32MHz
No. Of Timers
5
No. Of Pwm Channels
5
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, MA240013, AC164127, DM300027, DV164033, DM240002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Package
28SOIC W
Device Core
PIC
Family Name
PIC24
Maximum Speed
32 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164339 - MODULE SKT FOR PM3 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / Rohs Status
Details
9.0
The PIC24FJ64GA004 family of devices provides the
ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower
consumed power. All PIC24F devices manage power
consumption in four different ways:
• Clock frequency
• Instruction-based Sleep and Idle modes
• Software controlled Doze mode
• Selective peripheral control in software
Combinations of these methods can be used to selec-
tively tailor an application’s power consumption, while
still maintaining critical application features, such as
timing-sensitive communications.
9.1
PIC24F devices allow for a wide range of clock
frequencies to be selected under application control. If
the system clock configuration is not locked, users can
choose low-power or high-precision oscillators by simply
changing the NOSC bits. The process of changing a sys-
tem clock during operation, as well as limitations to the
process, are discussed in more detail in Section 8.0
“Oscillator Configuration”.
9.2
PIC24F devices have two special power-saving modes
that are entered through the execution of a special
PWRSAV instruction. Sleep mode stops clock operation
and halts all code execution; Idle mode halts the CPU
EXAMPLE 9-1:
2010 Microchip Technology Inc.
PWRSAV
PWRSAV
Note:
POWER-SAVING FEATURES
Clock Frequency and Clock
Switching
Instruction-Based Power-Saving
Modes
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
”Section 10. Power-Saving Features”
(DS39698). Additional power-saving tips
can also be found in Appendix B: “Addi-
tional Guidance for PIC24FJ64GA004
Family Applications” of this document.
#SLEEP_MODE
#IDLE_MODE
Family
PWRSAV INSTRUCTION SYNTAX
Reference
; Put the device into SLEEP mode
; Put the device into IDLE mode
Manual”,
PIC24FJ64GA004 FAMILY
and code execution, but allows peripheral modules to
continue operation. The assembly syntax of the
PWRSAV instruction is shown in Example 9-1.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset.
When the device exits these modes, it is said to
“wake-up”.
9.2.1
Sleep mode has these features:
• The system clock source is shut down. If an
• The device current consumption will be reduced
• The Fail-Safe Clock Monitor does not operate
• The LPRC clock will continue to run in Sleep
• The WDT, if enabled, is automatically cleared
• Some device features or peripherals may
The device will wake-up from Sleep mode on any of the
these events:
• On any interrupt source that is individually
• On any form of device Reset
• On a WDT time-out
On wake-up from Sleep, the processor will restart with
the same clock source that was active when Sleep
mode was entered.
on-chip oscillator is used, it is turned off.
to a minimum provided that no I/O pin is sourcing
current.
during Sleep mode since the system clock source
is disabled.
mode if the WDT is enabled.
prior to entering Sleep mode.
continue to operate in Sleep mode. This includes
items such as the input change notification on the
I/O ports, or peripherals that use an external clock
input. Any peripheral that requires the system
clock source for its operation will be disabled in
Sleep mode.
enabled
Note:
SLEEP MODE
SLEEP_MODE and IDLE_MODE are con-
stants defined in the assembler include
file for the selected device.
DS39881D-page 103