PIC12C672-10I/SM Microchip Technology, PIC12C672-10I/SM Datasheet - Page 73
PIC12C672-10I/SM
Manufacturer Part Number
PIC12C672-10I/SM
Description
IC MCU OTP 2KX14 A/D 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C672-10I/SM
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
For Use With
XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOICISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
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4.2
1997 Microchip Technology Inc.
OSC2/CLKOUT
(RC mode)
Clocking Scheme/Instruction Cycle
OSC1
Q4
PC
Q2
Q3
Q1
The clock input (from OSC1) is internally divided by four to generate four non-overlapping
quadrature clocks, namely Q1, Q2, Q3, and Q4. Internally, the program counter (PC) is incre-
mented every Q1, and the instruction is fetched from the program memory and latched into the
instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow are illustrated in
Example
Figure 4-3: Clock/Instruction Cycle
Q1
Execute INST (PC-1)
Fetch INST (PC)
Q2
T
4-1.
CY
PC
1
Q3
Q4
Q1
Execute INST (PC)
Fetch INST (PC+1)
Section 4. Architecture
Q2
T
PC+1
CY
2
Q3
Q4
Q1
Execute INST (PC+1)
Fetch INST (PC+2)
Q2
T
PC+2
CY
3
Q3
Q4
DS31004A-page 4-5
Figure
Internal
phase
clock
4-3, and
4
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