PIC18LF14K50-I/SO Microchip Technology, PIC18LF14K50-I/SO Datasheet
PIC18LF14K50-I/SO
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PIC18LF14K50-I/SO Summary of contents
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... USB Flash Microcontrollers with nanoWatt XLP™ Technology © 2009 Microchip Technology Inc. PIC18F13K50/14K50 Data Sheet Preliminary DS41350C ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Extended Watchdog Timer (WDT) - Programmable period from 4ms to 131s • Single-supply 3V In-Circuit Serial Program- ming™ (ICSP™) via two pins © 2009 Microchip Technology Inc. Extreme Low-Power Management PIC18LF1XK50 with nanoWatt XLP™: • Sleep Mode: 24nA • Watchdog Timer: 450nA • ...
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... PIC18LF13K50 PIC18F14K50/ 16K 8192 768 PIC18LF14K50 Note 1: One pin is input only. 2: Channel count includes internal Fixed Voltage Reference (FVR) and Programmable Voltage Reference (CV 3: Includes the dual port RAM used by the USB module which is shared with the data memory. ...
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... Packaging Information.............................................................................................................................................................. 393 Appendix A: Revision History............................................................................................................................................................. 397 Appendix B: Device Differences ........................................................................................................................................................ 397 Index .................................................................................................................................................................................................. 399 The Microchip Web Site ..................................................................................................................................................................... 409 Customer Change Notification Service .............................................................................................................................................. 409 Customer Support .............................................................................................................................................................................. 409 Reader Response .............................................................................................................................................................................. 410 Product Identification System ............................................................................................................................................................ 411 © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Preliminary DS41350C-page 3 ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS41350C-page 4 Preliminary © 2009 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F13K50 • PIC18F14K50 • PIC18LF13K50 • PIC18LF14K50 This family offers the advantages of all PIC18 microcontrollers – namely, high performance at an economical price – with the addition of high-endurance, Flash program memory. On top of ...
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... The devices are differentiated from each other in the following ways: 1. Flash program memory: • 8 Kbytes for PIC18F13K50/PIC18LF13K50 • 16 Kbytes for PIC18F14K50/PIC18LF14K50 2. On-chip 3.2V LDO regulator for PIC18F13K50 and PIC18F14K50. All other features for devices in this family are identical. These are summarized in Table 1-1. ...
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... DC – 48 MHz Ports MSSP, Enhanced USART, USB 9 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled 20-Pin PDIP, SSOP, SOIC (300 mil) Preliminary PIC18F14K50 PIC18LF14K50 Yes No 16K 8192 768 DS41350C-page 7 ...
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... Reference Timer0 Timer1 Timer2 USB MSSP EUSART Preliminary PORTA RA0 RA1 RA3 RA4 RA5 4 Access Bank 12 PORTB RB4 RB5 RB6 RB7 8 PRODL PORTC RC0 8 RC1 RC2 RC3 8 RC4 RC5 RC6 8 RC7 8 Timer3 FVR ADC CV 10-bit REF © 2009 Microchip Technology Inc. ...
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... RB6 SCK SCI RB7/TX/CK 10 RB7 TX CK Legend: TTL = TTL compatible input ST = Schmitt Trigger input O = Output XTAL= Crystal Oscillator © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Pin Buffer Type Type I TTL Digital input I/O XCVR USB differential plus line (input/output) I/O ST ICSP™ programming data pin ...
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... Ground reference for logic and I/O pins 1 P — Positive supply for logic and I/O pins P — Positive supply for USB transceiver CMOS = CMOS compatible input or output I = Input P = Power XCVR = USB Differential Transceiver Preliminary Description © 2009 Microchip Technology Inc. ...
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... CPU Clock Divider • USB Operation - Low Speed - Full Speed • Two-Speed Start-up Mode • Fail-Safe Clock Monitoring © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 2.2 System Clock Selection The SCS bits of the OSCCON register select between the following clock sources: • ...
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... MHz 110 4 MHz 101 2 MHz 100 1 MHz 011 500 kHz 010 250 kHz 001 31 kHz 1 000 0 INTSRC Fail-Safe Clock Watchdog Two-Speed Timer Start-up Preliminary IDLEN Sleep Peripherals System Clock CPU Sleep FOSC<3:0> Clock SCS<1:0> Control © 2009 Microchip Technology Inc. ...
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... HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 2-2 and Figure 2-3 show typical circuits for quartz crystal and ceramic resonators, respectively. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 FIGURE 2-2: C1 Quartz ...
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... The Secondary External Oscillator is designed to drive an external 32.768 kHz crystal. This oscillator is enabled or disabled by the T1OSCEN bit of the T1CON register. See Section 11.0 “Timer1 Module” for more information. Internal Clock Preliminary of the DD 0 – 250 kHz 4 – 48 MHz © 2009 Microchip Technology Inc. ...
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... MHZ • 1 MHZ (Default after Reset) • 500 kHz • 250 kHz • 31 kHz © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 The HFIOFS bit of the OSCCON register indicates whether the HFINTOSC is stable. Note 1: Selecting 31 kHz from the HFINTOSC oscillator requires IRCF<2:0> = 000 and the INTSRC bit of the OSCTUNE register to be set ...
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... Source selected by the INTSRC bit of the OSCTUNE register, see text. 3: Default output frequency of HFINTOSC on Reset. DS41350C-page 16 R/W-1 R-q R-0 (1) IRCF0 OSTS HFIOFS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 SCS1 SCS0 bit depends on condition x = Bit is unknown © 2009 Microchip Technology Inc. ...
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... HFIOFL: HFINTOSC Frequency Locked bit 1 = HFINTOSC is in lock 0 = HFINTOSC has not yet locked bit 0 LFIOFS: LFINTOSC Frequency Stable bit 1 = LFINTOSC is stable 0 = LFINTOSC is not stable © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 U-0 U-0 R/W-1 — — PRI_SD U = Unimplemented bit, read as ‘0’ ...
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... For more details about the function of the SPLLEN bit see Section 2.9 “4x Phase Lock Loop Frequency Multiplier” R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... New Clk Ready IRCF <2:0> Select Old System Clock Note 1: Start-up time includes T OST © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 2.8 Clock Switching The device contains circuitry to prevent clock “glitches” due to a change of the system clock source. To accomplish this, a short pause in the system clock occurs during the clock switch ...
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... USB module. To generate the 48 MHz clock, only 2 Oscillator modes are allowed: CONFIG1H • EC High-power mode • HS mode Table 2-5 shows the recommended Clock mode for full- speed operation. Preliminary Oscillator Delay Oscillator Warm-up Delay (T ) WARM 1024 clock cycles 8 Clock Cycles © 2009 Microchip Technology Inc. ...
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... EC High/HS 12 MHz Note: The system clock frequency in the above table only applies if the OSCCON register bits SCS<1:0> = 00. By changing these bits, the system clock can operate down to 31 kHz. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 4x PLL USBDIV CPUDIV<1:0> Enabled Yes 1 No ...
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... The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. Preliminary © 2009 Microchip Technology Inc. Clock Monitor Latch ...
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... Shaded cells are not used by oscillators. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 any type of Reset. The OST is not used with the Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed ...
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... PIC18F1XK50/PIC18LF1XK50 NOTES: DS41350C-page 24 Preliminary © 2009 Microchip Technology Inc. ...
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... Program Memory 2000h PIC18F13K50 PIC18F14K50 Read ‘0’ Read ‘0’ © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 3.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘ ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack <20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 Preliminary Stack Pointer STKPTR<4:0> 00010 © 2009 Microchip Technology Inc. ...
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... SP<4:0>: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 4.1 “Table Reads and Table Writes”. Preliminary © 2009 Microchip Technology Inc. nn ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 3.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Preliminary address embedded into the 0006h is encoded in the program Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2009 Microchip Technology Inc. ...
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... Additional information on USB RAM and buffer operation is provided in Section 22.0 “Universal Serial Bus (USB)” © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 3.3.2 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
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... Bank 0). The second 160 bytes are Special Function Registers (from Bank 15). When ‘a’ The BSR specifies the Bank used by the instruction. Access Bank 00h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh © 2009 Microchip Technology Inc. ...
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... FIGURE 3-6: DATA MEMORY MAP FOR PIC18F14K50/PIC18LF14K50 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh = 0101 00h Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 Bank 7 FFh ...
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... The MOVFF instruction embeds the entire 12-bit address in the instruction. DS41350C-page 34 Data Memory 000h 7 00h Bank 0 1 FFh 100h 00h Bank 1 FFh 200h 00h Bank 2 FFh 300h 00h Bank 3 through Bank 13 FFh E00h 00h Bank 14 FFh F00h 00h Bank 15 FFFh FFh Preliminary (2) From Opcode © 2009 Microchip Technology Inc. ...
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... The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section 3.5.3 “Mapping the Access Bank in Indexed Literal Offset Mode”. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 3.3.4 GENERAL PURPOSE REGISTER FILE PIC18 devices may have banked memory in the GPR area ...
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... UEP4 ANSEL F56h UEP3 (2) — F55h UEP2 (2) — F54h UEP1 (2) — F53h UEP0 IOCB IOCA WPUB WPUA SLRCON (2) — (2) — (2) — (2) — (2) — (2) — (2) — (2) — SRCON1 SRCON0 (2) — (2) — (2) — UCON USTAT UIR UCFG UIE © 2009 Microchip Technology Inc. ...
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... The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is read-only. 3: Bits RA0 and RA1 are available only when USB is disabled. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Bit 4 Bit 3 Bit 2 Top-of-Stack Upper Byte (TOS<20:16>) ...
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... STRA ---0 0001 281, 129 ABDEN 0100 0-00 281, 188 PDC0 0000 0000 281, 128 PSSBD0 0000 0000 281, 125 xxxx xxxx 281, 111 xxxx xxxx 281, 111 TMR3ON 0-00 0000 281, 109 © 2009 Microchip Technology Inc. ...
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... The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is read-only. 3: Bits RA0 and RA1 are available only when USB is disabled. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Bit 4 Bit 3 Bit 2 SYNC ...
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... PIDEE ---0 0000 283, 251 EPSTALL ---0 0000 283, 251 EPSTALL ---0 0000 283, 251 EPSTALL ---0 0000 283, 251 EPSTALL ---0 0000 283, 251 EPSTALL ---0 0000 283, 251 EPSTALL ---0 0000 283, 251 EPSTALL ---0 0000 279, 251 EPSTALL © 2009 Microchip Technology Inc. ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 It is recommended that only BCF, BSF, SWAPF, MOVFF ...
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... Example 3-5. EXAMPLE 3-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 BTFSS FSR0H, 1 BRA NEXT CONTINUE Preliminary © 2009 Microchip Technology Inc. ; Clear INDF ; register then ; inc pointer ; All done with ; Bank1? ; NO, clear next ; YES, continue ...
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... In this case, the FSR1 pair contains ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 3.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “ ...
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... Figure 3-9. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 25.2.1 “Extended Instruction Syntax”. Preliminary © 2009 Microchip Technology Inc. ...
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... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 000h 060h Bank 0 100h Bank 1 through ...
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... PIC18 instruction set. These instructions are executed as described in Section 25.2 “Extended Instruction Set”. Bank 0 Bank 1 Window Bank 1 Bank 2 through Bank 14 Bank 15 SFRs Data Memory Preliminary 00h Bank 1 “Window” 5Fh 60h SFRs FFh Access Bank © 2009 Microchip Technology Inc. ...
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... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 4.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... Then WR bit is cleared by hardware at the completion of the write operation. Note: The EEIF interrupt flag bit of the PIR2 register is set when the write is complete. The EEIF flag stays set until cleared by firmware. Preliminary Table Latch (8-bit) TABLAT © 2009 Microchip Technology Inc. ...
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... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 R/W-0 R/W-x R/W-0 ...
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... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 (1) TABLE READ – TBLPTR<21:0> Preliminary TBLPTRL 0 TABLE WRITE (1) TBLPTR<n:0> © 2009 Microchip Technology Inc. ...
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... TBLRD*+ MOVFW TABLAT, W MOVF WORD_ODD © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 4-4 shows the interface between the internal program memory and the TABLAT ...
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... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable block Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary © 2009 Microchip Technology Inc. ...
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... EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 The long write is necessary for programming the inter- nal Flash. Instruction execution is halted during a long write cycle ...
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... TBLWT holding register. Preliminary © 2009 Microchip Technology Inc. ...
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... C1IF PIE2 OSCFIE C1IE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 ; loop until holding registers are full ; point to Flash program memory ; access Flash program memory ; enable write to memory ...
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... PIC18F1XK50/PIC18LF1XK50 NOTES: DS41350C-page 56 Preliminary © 2009 Microchip Technology Inc. ...
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... EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 The EECON1 register (Register 5-1) is the control reg- ister for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory ...
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... When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS41350C-page 58 R/W-0 R/W-x R/W-0 FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/S-0 R/S bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... BSF EECON1, WR BSF INTCON, GIE BCF EECON1, WREN © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...
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... BCLIP USBIP C2IF EEIF BCLIF USBIF C2IE EEIE BCLIE USBIE Preliminary Reset Bit 1 Bit 0 Values on page INT0IF RABIF 279 281 EEADR9 EEADR8 281 281 281 WR RD 281 TMR3IP — 282 TMR3IF — 282 TMR3IE — 282 © 2009 Microchip Technology Inc. ...
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... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F1XK50 EXAMPLE 6- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
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... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2009 Microchip Technology Inc. ...
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... All interrupts branch to address 0008h in Compatibility mode. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 7.2 Interrupt Priority The interrupt priority feature is enabled by setting the IPEN bit of the RCON register ...
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... INT2IE INT2IP IPEN IPEN GIEL/PEIE IPEN TMR0IF TMR0IE TMR0IP (1) RABIF RABIE RABIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Preliminary © 2009 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h GIEH/GIE GIEL/PEIE ...
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... A mismatch condition will continue to set the RABIF bit. Reading PORTA and PORTB will end the mismatch condition and allow the bit to be cleared and RB port change interrupts also require the individual pin IOCA and IOCB enable. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Note: Interrupt flag bits are set when an interrupt ...
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... This feature allows for software polling. DS41350C-page 66 R/W-1 U-0 R/W-1 INTEDG2 — TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-1 — RABIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 R/W-0 R/W-0 U-0 INT2IE INT1IE U = Unimplemented bit, read as ‘ ...
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... R-0 R/W-0 R/W-0 TXIF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
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... USB has requested an interrupt (must be cleared in software USB interrupt request bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared by software TMR3 register did not overflow bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 R/W-0 R/W-0 R/W-0 EEIF BCLIF USBIF U = Unimplemented bit, read as ‘ ...
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... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS41350C-page 70 R/W-0 R/W-0 R/W-0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... USBIE: USB Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 R/W-0 R/W-0 R/W-0 EEIE BCLIE USBIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... Note 1: The PSPIF bit is unimplemented on 28-pin devices and will read as ‘0’. DS41350C-page 72 R/W-1 R/W-1 R/W-1 TXIP SSPIP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... USBIP: USB Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 R/W-1 R/W-1 R/W-1 EEIP BCLIP USBIP U = Unimplemented bit, read as ‘0’ ...
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... The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section 23.6 “Reset State of Registers” for additional information. 3: See Table 23-3. DS41350C-page 74 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (3) Preliminary R/W-0 R/W-0 (2) POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... USER ISR CODE ; MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 7.10 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF the 16-bit mode, an overflow in the TMR0H:TMR0L regis- ter pair (FFFFh → ...
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... PIC18F1XK50/PIC18LF1XK50 NOTES: DS41350C-page 76 Preliminary © 2009 Microchip Technology Inc. ...
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... Reset while a constant current source charges the external capacitor. After the cap is fully charged, the device is released from Reset. For more information, refer to Section 27.0 “Electrical Specifications”. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 from the ). ...
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... PIC18F1XK50/PIC18LF1XK50 NOTES: DS41350C-page 78 Preliminary © 2009 Microchip Technology Inc. ...
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... PORTA pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the PORT latch. ...
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... DS41350C-page 80 EXAMPLE 9-1: INITIALIZING PORTA CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches CLRF LATA ; Alternate method ; to clear output ; data latches MOVLW 030h ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<5:4> as output Preliminary © 2009 Microchip Technology Inc. ...
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... TRISA<5:4>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated PORTA pin configured as an output bit 3-0 Unimplemented: Read as ‘0’ Note 1: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 R/W-x R-x U-0 RA4 RA3 U = Unimplemented bit, read as ‘ ...
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... U-0 U-0 LATA4 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit Bit is unknown R/W-0 R/W-0 IOCA1 IOCA0 bit Bit is unknown U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Note 1: RA0 and RA1 do not have corresponding TRISA bits. In Port mode, these pins are input only. USB data direction is determined by the USB configuration. 2: RA3 does not have a corresponding TRISA bit. This pin is always an input regardless of mode. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 I/O ...
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... Reset Bit 1 Bit 0 Values on page (3) (3) RA1 RA0 282 — — 282 — — 282 — — 282 SLRB SLRA 282 (3) (3) 282 IOCA1 IOCA0 — — 282 — 282 INT0IF RABIF 279 — RABIP 279 © 2009 Microchip Technology Inc. ...
Page 87
... A mismatch condition will continue to set the RABIF flag bit. Reading or writing PORTB will end the mismatch condition and allow the RABIF bit to be cleared. The latch © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 holding the last read value is not affected by a MCLR nor Brown-out Reset ...
Page 88
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 U-0 U-0 TRISB4 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit Bit is unknown U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 89
... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-4 LATB<7:4>: RB<7:4> Port I/O Output Latch Register bits bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 R/W-1 U-0 U-0 WPUB4 — Unimplemented bit, read as ‘0’ ...
Page 90
... Asynchronous serial transmit data output (USART module); takes priority over port data. User must configure as output. O DIG Synchronous serial clock output (USART module); takes priority over port data Synchronous serial clock input (USART module). Preliminary Description © 2009 Microchip Technology Inc. ...
Page 91
... ANSELH — — TXSTA CSRC TX9 RCSTA SPEN RX9 SSPCON1 WCOL SSPOV Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 — — LATB5 LATB4 — ...
Page 92
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 R/W-1 TRISC4 TRISC3 TRISC2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-x R/W-x RC1 RC0 bit Bit is unknown R/W-1 R/W-1 TRISC1 TRISC0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 93
... LATC5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 LATC<7:0>: RB<7:0> Port I/O Output Latch Register bits © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 R/W-x R/W-x R/W-x LATC4 LATC3 LATC2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 94
... LATC<4> data output PORTC<4> data input. O DIG Comparator 1 and 2 output; takes priority over port data. O DIG ECCP1 Enhanced PWM output, channel B. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. Preliminary Description © 2009 Microchip Technology Inc. ...
Page 95
... SLRCON — — REFCON1 D1EN D1LPS INTCON GIE/GIEH PEIE/GIEL INTCON2 RABPU INTEDG0 INTCON3 INT2IP INT1IP © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 I/O I/O Type O DIG LATC<5> data output PORTC<5> data input. O DIG ECCP1 compare or PWM output; takes priority over port data. ...
Page 96
... ANSx bit set will still operate as a digital output but the Input mode will be analog. R/W-1 R/W-1 U-0 ANS4 ANS3 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 97
... ANS9: RC7 Analog Select Control bit 1 = Digital input buffer of RC7 is disabled 0 = Digital input buffer of RC7 is enabled bit 0 ANS8: RC6 Analog Select Control bit 1 = Digital input buffer of RC6 is disabled 0 = Digital input buffer of RC6 is enabled © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 U-0 R/W-1 R/W-1 — ANS11 ANS10 U = Unimplemented bit, read as ‘ ...
Page 98
... Note 1: The slew rate of RA4 defaults to standard rate when the pin is used as CLKOUT. DS41350C-page 96 U-0 U-0 R/W-1 — — SLRC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary © 2009 Microchip Technology Inc. R/W-1 R/W-1 SLRB SLRA bit Bit is unknown ...
Page 99
... Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 The T0CON register (Register 10-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. ...
Page 100
... Timer0 is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. ). OSC 0 Sync with Internal Clocks Programmable 1 Prescaler (2 T Delay Preliminary Set TMR0IF TMR0L on Overflow 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
Page 101
... TRISC6 Legend: Shaded cells are not used by Timer0. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 0 Sync with Internal TMR0L ...
Page 102
... PIC18F1XK50/PIC18LF1XK50 NOTES: DS41350C-page 100 Preliminary © 2009 Microchip Technology Inc. ...
Page 103
... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 A simplified block diagram of the Timer1 module is shown in Figure 11-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 11-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 104
... When the bit is set, Timer1 OSC 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
Page 105
... XTAL 32.768 kHz T1OSO Note: See the Notes with Table 11-1 for additional information about capacitor selection. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 TABLE 11-1: Osc Type LP Note 1: Microchip suggests these values only as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator but also increases the start-up time ...
Page 106
... In the event that a write to Timer1 coincides with a special Event Trigger, the write operation will take precedence. Note: The Special Event Triggers from the CCP2 module will not set the TMR1IF interrupt flag bit of the PIR1 register. Preliminary © 2009 Microchip Technology Inc. ...
Page 107
... CPFSGT hours RETURN CLRF hours RETURN © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Since the register pair is 16 bits wide, a 32.768 kHz clock source will take 2 seconds to count up to over- flow. To force the overflow at the required one-second intervals necessary to preload it; the simplest method is to set the MSb of TMR1H with a BSF instruc- tion ...
Page 108
... SSPEN CKP SSPM3 SSPM2 Preliminary Reset Bit 1 Bit 0 Values on page INT0IF RABIF 279 TMR2IF TMR1IF 282 TMR2IE TMR1IE 282 TMR2IP TMR1IP 282 280 280 TMR1CS TMR1ON 280 TRISC1 TRISC0 282 ANS9 ANS8 282 SSPM1 SSPM0 280 © 2009 Microchip Technology Inc. ...
Page 109
... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 12.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
Page 110
... SSPIF CCP1IF TXIE SSPIE CCP1IE TXIP SSPIP CCP1IP Preliminary Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RABIF 279 TMR2IF TMR1IF 282 TMR2IE TMR1IE 282 TMR2IP TMR1IP 282 280 280 280 © 2009 Microchip Technology Inc. ...
Page 111
... OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 A simplified block diagram of the Timer3 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. The Timer3 module is controlled through the T3CON register (Register 13-1) ...
Page 112
... TRISC<1:0> are ignored and the pins are read as ‘0’. Timer1 Clock Input 1 Prescaler F /4 OSC Internal 0 Clock 2 TMR3CS Clear TMR3 TMR3L Preliminary /4). When the bit is set, Timer3 OSC 1 Synchronize Detect 0 Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow © 2009 Microchip Technology Inc. ...
Page 113
... The high byte of Timer3 is not directly readable or writable in this mode. All reads and writes must take place through the Timer3 High Byte Buffer register. Writes to TMR3H do not clear the Timer3 prescaler. The prescaler is only cleared on writes to TMR3L. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Timer1 Clock Input 1 Prescaler ...
Page 114
... ANS11 ANS10 Preliminary Reset Bit 1 Bit 0 Values on page INT0IF RABIF 279 TMR3IF CCP2IF 282 TMR3IE CCP2IE 282 TMR3IP CCP2IP 282 281 281 TMR1CS TMR1ON 280 TMR3CS TMR3ON 281 TRISC1 TRISC0 282 ANS9 ANS8 282 © 2009 Microchip Technology Inc. ...
Page 115
... PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 CCP1 is implemented as a standard CCP module with enhanced PWM capabilities. These include: • ...
Page 116
... The assignment of a particular timer to a module is determined by the Timer-to-CCP enable bits in the T3CON register (Register 13-1). The interactions between the two modules are Figure 14-1. In Asynchronous Counter mode, the capture operation will not work reliably. DS41350C-page 114 summarized in Preliminary © 2009 Microchip Technology Inc. ...
Page 117
... FIGURE 14-1: CAPTURE MODE OPERATION BLOCK DIAGRAM CCP1 pin Prescaler ÷ CCP1CON<3:0> Q1:Q4 © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 be used with each CCP module is selected in the T3CON register (see Section 14.1.1 “CCP Module and Timer Resources”). 14.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated ...
Page 118
... The Special Event Trigger can also start an A/D conver- sion. In order to do this, the A/D converter must already be enabled. Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) Set CCP1IF Compare Output Match Logic 4 CCP1CON<3:0> Preliminary Special Event Trigger mode CCP1 pin TRIS Output Enable © 2009 Microchip Technology Inc. ...
Page 119
... Full-Bridge, Reverse 11 Note 1: Outputs are enabled by pulse steering in Single mode. See Register 14-4. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately ...
Page 120
... Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 14.4.6 “Programmable Dead-Band Delay mode”). DS41350C-page 118 Pulse 0 Width Period (1) (1) Delay Delay Preliminary © 2009 Microchip Technology Inc. PR2+1 ...
Page 121
... OSC • Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 14.4.6 “Programmable Dead-Band Delay mode”). © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Pulse 0 Width Period (1) (1) Delay Delay ...
Page 122
... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. FET Driver P1A Load FET Driver P1B V+ FET Driver Load FET Driver Preliminary EXAMPLE OF HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2009 Microchip Technology Inc. ...
Page 123
... P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. FIGURE 14-8: EXAMPLE OF FULL-BRIDGE APPLICATION P1A P1B P1C P1D © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 V+ QA FET Driver Load FET Driver QB ...
Page 124
... Forward Mode (2) P1A Pulse Width (2) P1B (2) P1C (2) P1D (1) Reverse Mode Pulse Width (2) P1A (2) P1B (2) P1C (2) P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high. DS41350C-page 122 Period (1) Period (1) Preliminary © 2009 Microchip Technology Inc. ...
Page 125
... When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is (1/F value. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 The Full-Bridge mode does not provide dead-band delay ...
Page 126
... PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. DS41350C-page 124 Forward Period Reverse Period Preliminary PW OFF – T OFF ON © 2009 Microchip Technology Inc. ...
Page 127
... PSSBDn: Pins P1B and P1D Shutdown State Control bits 00 = Drive pins P1B and P1D to ‘0’ Drive pins P1B and P1D to ‘1’ Pins P1B and P1D tri-state © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a ‘ ...
Page 128
... Activity Start of PWM Period DS41350C-page 126 is a condition PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears Preliminary ECCPASE Cleared by Firmware PWM Resumes PWM Resumes © 2009 Microchip Technology Inc. ...
Page 129
... The lower seven bits of the associated PWM1CON register (Register 14-3) sets the delay period in terms of microcontroller instruction cycles ( OSC FIGURE 14-15: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 FIGURE 14-14: Period Pulse Width (2) P1A td (2) P1B (1) ...
Page 130
... DS41350C-page 128 R/W-0 R/W-0 PDC4 PDC3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared / cycles between the scheduled time when a PWM signal OSC OSC Preliminary R/W-0 R/W-0 R/W-0 PDC2 PDC1 PDC0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 131
... P1A pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2> and P1M<1:0> = 00. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Note: The associated TRIS bits must be set to output (‘0’) to enable the pin output driver in order to see the PWM signal on the pin. While the PWM Steering mode is active, CCP1M< ...
Page 132
... Note 1: Port outputs are configured as shown when the CCP1CON register bits P1M<1:0> and CCP1M<3:2> = 11. 2: Single PWM output requires setting at least one of the STRx bits. DS41350C-page 130 P1A pin P1B pin P1C pin P1D pin Preliminary © 2009 Microchip Technology Inc. ...
Page 133
... PORT Data FIGURE 14-18: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1) PWM STRn P1<D:A> PORT Data © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Figures 14-17 and 14-18 illustrate the timing diagrams of the PWM steering depending on the STRSYNC setting. P1n = PWM P1n = PWM Preliminary ...
Page 134
... Both Power-on Reset and subsequent Resets will force all ports to Input mode and the CCP registers to their Reset states. This forces the enhanced CCP module to reset to a state compatible with the standard CCP module. DS41350C-page 132 Preliminary © 2009 Microchip Technology Inc. ...
Page 135
... Capture/Compare/PWM Register 1, High Byte CCP1CON P1M1 P1M0 ECCP1AS ECCPASE ECCPAS2 PWM1CON PRSEN PDC6 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Bit 5 Bit 4 Bit 3 TMR0IE INT0IE RABIE TMR0IF — RI ...
Page 136
... PIC18F1XK50/PIC18LF1XK50 NOTES: DS41350C-page 134 Preliminary © 2009 Microchip Technology Inc. ...
Page 137
... The I C interface supports the following modes in hardware: • Master mode • Multi-Master mode • Slave mode © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 15.2 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes ...
Page 138
... SSPIF interrupt is set. During transmission, double-buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary the SSPBUF is not R-0 R bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 139
... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 R/W-0 R/W-0 R/W-0 CKP ...
Page 140
... Example 15-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP STATUS register (SSPSTAT) indicates the various status conditions. Preliminary © 2009 Microchip Technology Inc. ...
Page 141
... Shift Register (SSPSR) LSb MSb General I/O Processor 1 © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 15.2.4 TYPICAL CONNECTION Figure 15-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...
Page 142
... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 2 bit 5 bit 4 bit 1 bit 3 bit 2 bit 5 bit 4 bit 3 bit 1 Preliminary give waveforms for SPI ) Clock Modes bit 0 bit 0 bit 0 bit 0 © 2009 Microchip Technology Inc. ...
Page 143
... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 15.2.7 SLAVE SELECT SYNCHRONIZATION The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPCON1<3:0> = 0100). When the SS pin is low, transmission and reception are enabled and the SDO pin is driven ...
Page 144
... CKE = 1) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS41350C-page 142 bit 6 bit 3 bit 2 bit 5 bit 4 bit 6 bit 3 bit 2 bit 5 bit 4 Preliminary ) 0 bit 1 bit 0 bit 0 bit 1 bit 0 bit 0 © 2009 Microchip Technology Inc. ...
Page 145
... SSPSTAT SMP CKE Legend: Shaded cells are not used by the MSSP in SPI mode. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Transmit/Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. ...
Page 146
... SSPBUF Addr Match and the SSPIF interrupt is set. During transmission, double-buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT Reg) Preliminary mode operation. The 2 C the SSPBUF is not © 2009 Microchip Technology Inc. ...
Page 147
... This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the Master mode is active. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 2 C MODE) ...
Page 148
... DS41350C-page 146 2 C MODE) R/W-0 R/W-0 R/W-0 CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C conditions were not valid for a trans- /(4 * (SSPADD + 1)) OSC Preliminary R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 149
... For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). 2: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 2 C MODE) ...
Page 150
... SSPIF, BF, R/W are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit, SSPIF. 10. Load SSPBUF with byte the slave is to transmit, sets the BF bit. 11. Set the CKP bit to release SCL. Preliminary Addressing © 2009 Microchip Technology Inc. ...
Page 151
... The clock must be released by setting the CKP bit of the SSPCON1 register. See Section 15.3.4 “Clock Stretching” for more detail. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 15.3.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
Page 152
... PIC18F1XK50/PIC18LF1XK50 2 FIGURE 15-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS41350C-page 150 Preliminary © 2009 Microchip Technology Inc. ...
Page 153
... FIGURE 15-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Preliminary DS41350C-page 151 ...
Page 154
... PIC18F1XK50/PIC18LF1XK50 2 FIGURE 15-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS41350C-page 152 Preliminary © 2009 Microchip Technology Inc. ...
Page 155
... FIGURE 15-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Preliminary DS41350C-page 153 ...
Page 156
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C address match 2 (1) C Slave mode, 10-bit Address 2 C address match Preliminary 2 C Slave mode (7-bit or R/W-1 R/W-1 (1) MSK1 MSK0 bit Bit is unknown 2 C address match 2 C address match © 2009 Microchip Technology Inc. ...
Page 157
... ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<6:0>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care.” © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 R/W-0 R/W-0 R/W-0 ADD4 ADD3 ADD2 U = Unimplemented bit, read as ‘ ...
Page 158
... UA bit is not set, the module is now configured in Transmit mode and clock stretching is automatic with the hard- ware clearing CKP 7-bit Slave Transmit mode (see Figure 15-11). Preliminary data transfer sequence (see © 2009 Microchip Technology Inc. ...
Page 159
... CKP bit will not violate the minimum high time requirement for SCL (see Figure 15-12). FIGURE 15-12: CLOCK SYNCHRONIZATION TIMING SDA DX SCL CKP WR SSPCON1 © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Master device asserts clock Master device deasserts clock Preliminary DX – 1 DS41350C-page 157 ...
Page 160
... PIC18F1XK50/PIC18LF1XK50 2 FIGURE 15-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS41350C-page 158 Preliminary © 2009 Microchip Technology Inc. ...
Page 161
... FIGURE 15-14: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Preliminary DS41350C-page 159 ...
Page 162
... Acknowledge (Figure 15-15). Address is compared to General Call Address after ACK, set interrupt R ACK Cleared by software SSPBUF is read Preliminary Receiving Data ACK ‘0’ ‘1’ © 2009 Microchip Technology Inc. ...
Page 163
... Generate a Stop condition on SDA and SCL. FIGURE 15-16: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not ...
Page 164
... ACKSTAT bit of the SSPCON2 register. 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the PEN bit of the SSPCON2 register. 12. Interrupt is generated once the Stop condition is complete. Preliminary © 2009 Microchip Technology Inc. ...
Page 165
... The I C interface does not conform to the 400 kHz I 100 kHz) in all details, but may be used with care where higher rates are required by the application. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Table 15-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD ...
Page 166
... BRG 03h Value BRG Reload DS41350C-page 164 DX – 1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count Preliminary 03h 02h © 2009 Microchip Technology Inc. ...
Page 167
... Start condition is complete. FIGURE 15-19: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Note the beginning of the Start condition, the SDA and SCL pins are already sam- pled low during the Start condition, the ...
Page 168
... SSPCON2 is disabled until the Repeated Start condition is complete. S bit set by hardware SDA = 1, At completion of Start bit, SCL = 1 hardware clears RSEN bit and sets SSPIF BRG BRG BRG Write to SSPBUF occurs here T BRG Sr = Repeated Start Preliminary 1st bit T BRG © 2009 Microchip Technology Inc. ...
Page 169
... WCOL is set and the contents of the buf- fer are unchanged (the write doesn’t occur). WCOL must be cleared by software before the next transmission. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 15.3.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit of the SSPCON2 ...
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... PIC18F1XK50/PIC18LF1XK50 2 FIGURE 15-21: I C™ MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS41350C-page 168 Preliminary © 2009 Microchip Technology Inc. ...
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... FIGURE 15-22: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Preliminary DS41350C-page 169 ...
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... BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to setup Stop condition Preliminary (Baud Rate Generator rollover count) later, the PEN bit is BRG WCOL Status Flag ACKEN automatically cleared Cleared in software BRG © 2009 Microchip Technology Inc. ...
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... FIGURE 15-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA SCL BCLIF © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 15.3.17 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitra- tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘ ...
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... Repeated Start or Stop conditions. SEN cleared automatically because of bus collision. SSP module reset into Idle state. SSPIF and BCLIF are cleared by software SSPIF and BCLIF are cleared by software Preliminary © 2009 Microchip Technology Inc. ...
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... BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION Less than T SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL SEN BCLIF S SSPIF © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 SDA = 0, SCL = BRG BRG SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SDA = 0, SCL = 1 ...
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... Repeated Start condition is complete. Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. Cleared by software T T BRG BRG Preliminary © 2009 Microchip Technology Inc. ‘0’ ‘0’ Interrupt cleared by software ‘0’ ...
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... SCL PEN BCLIF P SSPIF © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD and counts down to 0 ...
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... TMR2IF TMR1IF 282 TMR2IE TMR1IE 282 282 – TMR3IP 282 – TMR3IF 282 – TMR3IE 2 C Master Mode. 280 280 SSPM1 SSPM0 280 RSEN SEN 280 MSK1 MSK0 282 UA BF 280 282 – – – © 2009 Microchip Technology Inc. ...
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... SPBRGH SPBRG BRGH BRG16 © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 The EUSART module includes the following capabilities: • Full-duplex asynchronous transmit and receive • Two-character input buffer • One-character output buffer • Programmable 8-bit or 9-bit character length • Address detection in 9-bit mode • ...
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... DS41350C-page 178 MSb Data Stop Recovery F OSC ÷ x16 x64 0 0 FERR 0 Register 16-1, Preliminary CREN OERR RCIDL RSR Register LSb • • • (8) 7 START 1 0 RX9 FIFO RX9D RCREG Register 8 Data Bus RCIF Interrupt RCIE © 2009 Microchip Technology Inc. ...
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... TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral the analog I/O function must be disabled by clearing the corresponding ANSEL bit. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Note 1: When the SPEN bit is set the RX/DT I/O pin is automatically configured as an input, ...
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... CON register are also set 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. 8. Load 8-bit data into the TXREG register. This will start the transmission. bit 0 bit 1 bit 7/8 Word 1 Preliminary Stop bit © 2009 Microchip Technology Inc. ...
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... RCIDL SPBRGH EUSART Baud Rate Generator Register, High Byte SPBRG EUSART Baud Rate Generator Register, Low Byte Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 bit 0 bit 1 Word ...
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... Setting the DTRXP bit to ‘1’ will invert the receive data resulting in low true idle and data bits. The DTRXP bit controls receive data polarity only in Asynchronous mode. In synchronous mode the DTRXP bit has a different function. Preliminary Receiving Data Receive Data Polarity © 2009 Microchip Technology Inc. ...
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... The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 16.1.2.7 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When ...
Page 186
... If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. Start bit 7/8 bit 7/8 Stop Stop bit bit 0 bit bit Word 2 Word 1 RCREG RCREG Preliminary Start bit Stop bit 7/8 bit © 2009 Microchip Technology Inc. ...
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... SPBRGH EUSART Baud Rate Generator Register, High Byte SPBRG EUSART Baud Rate Generator Register, Low Byte Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Bit 5 Bit 4 Bit 3 Bit 2 ...
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... Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. R/W-0 R/W-0 (1) SYNC SENDB U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary feature (see Section 16.3.1 R/W-0 R-1 R/W-0 BRGH TRMT TX9D bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 R/W-0 R/W-0 R-0 CREN ...
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... Auto-Baud Detect mode is enabled (clears when auto-baud is complete Auto-Baud Detect mode is disabled Synchronous mode: Don’t care DS41350C-page 188 R/W-0 R/W-0 U-0 CKTXP BRG16 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 WUE ABDEN bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... SPBRG EUSART Baud Rate Generator Register, Low Byte Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 If the system clock is changed during an active receive operation, a receive error or data loss may result. To ...
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... F = 11.0592 MHz OSC SPBRG SPBRG Actual % value value Rate Error (decimal) (decimal) — — — — — — — — — — — — 77 9600 0. 10473 0. 19.20k 0. 57.60k 0.00 11 — 115.2k 0.00 5 © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 SYNC = 0, BRGH = 1, BRG16 = 4.000 MHz F = 3.6864 MHz OSC OSC SPBRG % Actual % value Rate Error Rate Error (decimal) — — ...
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... F = 1.000 MHz OSC SPBRGH SPBRGH Actual % :SPBRG :SPBRG Rate Error (decimal) (decimal) 3071 300.1 0.04 832 767 1202 0.16 207 383 2404 0.16 103 95 9615 0. 10417 0. 19.23k 0. — — — 7 — — — © 2009 Microchip Technology Inc. ...
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... SPBRG SPBRGH Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 and SPBRG registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. ...
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... To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. Preliminary © 2009 Microchip Technology Inc. ...
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... If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 Cleared due to User Read of RCREG Q1 ...
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... Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDCON register before placing the EUSART in Sleep mode. bit 0 bit 1 bit 11 Break Auto Cleared Preliminary © 2009 Microchip Technology Inc. Stop bit ...
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... One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. © 2009 Microchip Technology Inc. PIC18F1XK50/PIC18LF1XK50 16.4.1.2 Clock Polarity A clock polarity option is provided for Microwire compatibility ...
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... PEIE interrupt enable bits 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. 8. Start transmission by loading data to the TXREG register. bit 2 bit 7 bit 0 bit 1 Word 2 bit 0 bit 2 bit 1 Preliminary bit 7 ‘1’ bit 6 bit 7 © 2009 Microchip Technology Inc. ...