PIC18LF24J50-I/SO Microchip Technology, PIC18LF24J50-I/SO Datasheet - Page 165
![IC PIC MCU FLASH 16K 2V 28-SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18LF24J50-I/SO
Manufacturer Part Number
PIC18LF24J50-I/SO
Description
IC PIC MCU FLASH 16K 2V 28-SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18LF24J50-I/SO
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
16
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
16
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, MA180024, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- Current page: 165 of 554
- Download datasheet (9Mb)
REGISTER 10-2:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
CSF1
2:
This register is only available in 44-pin devices.
These bits have no effect when their corresponding pins are used as address lines.
CSF<1:0>: Chip Select Function bits
11 = Reserved
10 = Chip select function is enabled and PMCS acts as chip select (in Master mode). Up to
01 = Reserved
00 = Chip select function is disabled (in Master mode). All 16 address bits can be generated.
ALP: Address Latch Polarity bit
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
Unimplemented: Maintain as ‘0’
CS1P: Chip Select Polarity bit
1 = Active-high (PMCS)
0 = Active-low (PMCS)
BEP: Byte Enable Polarity bit
1 = Byte enable active-high (PMBE)
0 = Byte enable active-low (PMBE)
WRSP: Write Strobe Polarity bit
For Slave modes and Master Mode 2 (PMMODEH<1:0> = 00,01,10):
1 = Write strobe active-high (PMWR)
0 = Write strobe active-low (PMWR)
For Master Mode 1 (PMMODEH<1:0> = 11):
1 = Enable strobe active-high (PMENB)
0 = Enable strobe active-low (PMENB)
RDSP: Read Strobe Polarity bit
For Slave modes and Master Mode 2 (PMMODEH<1:0> = 00,01,10):
1 = Read strobe active-high (PMRD)
0 = Read strobe active-low (PMRD)
For Master Mode 1 (PMMODEH<1:0> = 11):
1 = Read/write strobe active-high (PMRD/PMWR)
0 = Read/write strobe active-low (PMRD/PMWR)
R/W-0
CSF0
13 address bits only can be generated.
PMCONL: PARALLEL PORT CONTROL REGISTER LOW BYTE (BANKED F5Eh)
W = Writable bit
‘1’ = Bit is set
R/W-0
ALP
(2)
(2)
(2)
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F46J50 FAMILY
R/W-0
CS1P
(2)
R/W-0
BEP
x = Bit is unknown
WRSP
R/W-0
DS39931C-page 165
R/W-0
RDSP
bit 0
(1)
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