PIC16F628-20/P Microchip Technology, PIC16F628-20/P Datasheet - Page 36
![IC MCU FLASH 2KX14 COMP 18DIP](/photos/6/76/67657/18-dip_300mil__sml.jpg)
PIC16F628-20/P
Manufacturer Part Number
PIC16F628-20/P
Description
IC MCU FLASH 2KX14 COMP 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC16F627-04P.pdf
(170 pages)
Specifications of PIC16F628-20/P
Program Memory Type
FLASH
Program Memory Size
3.5KB (2K x 14)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
224 B
Interface Type
SCI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
0 C
Data Rom Size
128 B
Height
3.3 mm
Length
22.86 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
3 V
Width
6.35 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA16XP183 - ADAPTER ICE 18DIP/SOIC/SSOPAC164010 - MODULE SKT PROMATEII DIP/SOIC
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
PIC16F62X
TABLE 5-2:
5.2
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. A '1' in
the TRISB register puts the corresponding output driver
in a Hi-impedance mode. A '0' in the TRISB register
puts the contents of the output latch on the selected
pin(s).
PORTB is multiplexed with the external interrupt,
USART, CCP module and the TMR1 clock input/output.
The standard port functions and the alternate port
functions are shown in Table 5-3. Alternate port
functions override TRIS setting when enabled.
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
Each of the PORTB pins has a weak internal pull-up
(≈200 µA typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Four of PORTB’s pins, RB<7:4>, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB<7:4> pin con-
figured as an output is excluded from the interrupt-on-
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RBIF interrupt (flag
latched in INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
DS40300C-page 34
05h
85h
1Fh
9Fh
Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown
Note 1: Shaded bits are not used by PORTA.
Address
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
PORTB and TRISB Registers
PORTA
TRISA
CMCON
VRCON
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
TRISA7
C2OUT
VREN
Bit 7
RA7
TRISA6
C1OUT
VROE
Bit 6
RA6
TRISA5 TRISA4
C2INV
Bit 5
VRR
RA5
C1INV
Bit 4
RA4
Preliminary
—
TRISA3
Bit 3
RA3
VR3
CIS
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression. (See AN552)
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Note:
TRISA2
Bit 2
CM2
RA2
VR2
If a change on the I/O pin should occur
when a read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
TRISA1
Bit 1
CM1
VR1
RA1
(1)
TRISA0
Bit 0
CM0
RA0
VR0
2003 Microchip Technology Inc.
xxxx 0000
1111 1111
0000 0000
000- 0000
Value on
POR
xxxu 0000
1111 1111
0000 0000
000- 0000
All Other
Value on
RESETS