PIC16LF818-I/ML Microchip Technology, PIC16LF818-I/ML Datasheet - Page 88

• Manufacturer Part Number: PIC16LF818-I/ML
• Description: IC MCU FLASH 1KX14 EEPROM 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF818-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F818/819
11.4
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2-T
acquisition is started. After this 2-T
on the selected channel is automatically started. The
GO/DONE bit can then be set to start the conversion.
In Figure 11-3, after the GO bit is set, the first time
segment has a minimum of T
FIGURE 11-3:
FIGURE 11-4:
DS39598D-page 86
Note:
A/D Conversions
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
T
CY
Set GO bit
Holding Capacitor is disconnected from analog input (typically 100 ns)
7
to T
AD
0000 00
ADRESH
AD
wait is required before the next
Conversion starts
A/D CONVERSION T
A/D RESULT JUSTIFICATION
T
AD
Right Justified
1
CY
2 1 0 7
ADFM = 1
and a maximum of T
T
AD
b9
2
10-bit Result
AD
T
ADRESL
AD
b8
wait, acquisition
3
T
AD
b7
AD
4
0
AD
CYCLES
T
AD
b6
.
10-bit Result
5
T
AD
b5
6
11.4.1
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16 bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 11-4 shows the operation of the A/D result
justification. The extra bits are loaded with ‘0’s. When
an A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
ADRES is loaded,
GO bit is cleared,
ADIF bit is set,
Holding Capacitor is connected to analog input
T
AD
b4
7
7
T
AD
b3
ADRESH
10-bit Result
8
A/D RESULT REGISTERS
T
AD
b2
Left Justified
ADFM = 0
9
T
0 7 6 5
AD
b1
10 T
 2003 Microchip Technology Inc.
ADRESL
AD
0000 00
b0
11
0