PIC16F916-I/SO Microchip Technology, PIC16F916-I/SO Datasheet - Page 143
![IC PIC MCU FLASH 8KX14 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC16F916-I/SO
Manufacturer Part Number
PIC16F916-I/SO
Description
IC PIC MCU FLASH 8KX14 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F913-ISS.pdf
(330 pages)
3.PIC16F913-ISS.pdf
(8 pages)
4.PIC16F913-ISS.pdf
(34 pages)
5.PIC16F913-ISO.pdf
(274 pages)
Specifications of PIC16F916-I/SO
Program Memory Type
FLASH
Program Memory Size
14KB (8K x 14)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
352 B
Interface Type
SSP/I2C/AUSART/SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120
Minimum Operating Temperature
- 40 C
On-chip Adc
5-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F916-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F913-ISS PDF datasheet #2
- PIC16F913-ISS PDF datasheet #3
- PIC16F913-ISS PDF datasheet #4
- PIC16F913-ISO PDF datasheet #5
- Current page: 143 of 274
- Download datasheet (5Mb)
FIGURE 11-11:
11.4
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK/SCK/SCL/SEG9 pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in Sleep mode.
Slave mode is entered by clearing bit, CSRC
(TXSTA<7>).
11.4.1
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
2004 Microchip Technology Inc.
SDI/SDA/SEG8
RC6/TX/CK/
SCK/SCL/SEG9
RC7/RX/DT/
(Interrupt)
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
If enable bit TXIE is set, the interrupt will wake
the chip from Sleep and if the global interrupt is
enabled, the program will branch to the interrupt
vector (0004h).
CREN bit
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
bit SREN
SREN bit
RCIF bit
RXREG
Write to
Read
USART Synchronous Slave Mode
Q2
USART SYNCHRONOUS SLAVE
TRANSMIT
Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
‘0’
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit 0
Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4
bit 1
bit 2
Preliminary
bit 3
When setting up a Synchronous Slave Transmission,
follow these steps:
1.
2.
3.
4.
5.
6.
7.
8.
bit 4
Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
bit 5
bit 6
PIC16F91X
bit 7
DS41250B-page 141
Q1Q2Q3Q4
‘0’
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