PIC24FJ32GA002-I/SS Microchip Technology, PIC24FJ32GA002-I/SS Datasheet - Page 48
![IC PIC MCU FLASH 32K 28-SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC24FJ32GA002-I/SS
Manufacturer Part Number
PIC24FJ32GA002-I/SS
Description
IC PIC MCU FLASH 32K 28-SSOP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ16GA002-ISS.pdf
(268 pages)
3.PIC24FJ16GA002-ISS.pdf
(22 pages)
4.PIC24FJ64GA004-EPT.pdf
(262 pages)
Specifications of PIC24FJ32GA002-I/SS
Program Memory Type
FLASH
Program Memory Size
32KB (11K x 24)
Package / Case
28-SSOP
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C/IrDA/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DM300027, DV164033, MA240013, AC164127, DM240002
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Controller Family/series
PIC24
No. Of I/o's
21
Ram Memory Size
8KB
Cpu Speed
32MHz
No. Of Timers
5
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164338 - MOD SKT PIC24F/DSPIC33F 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24FJ32GA002-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC24FJXXXGA0XX
TABLE 6-4:
DS39768D-page 48
PIC24FJ128GAGA006
PIC24FJ128GAGA008
PIC24FJ128GAGA010
Legend:
Note:
Device
Item
SUM[a:b]
CFGB
CW1 address is last location of implemented program memory; CW2 is (last location – 2).
CHECKSUM COMPUTATION (CONTINUED)
=
=
Description
Byte sum of locations, a to b inclusive (all 3 bytes of code memory)
Configuration Block (masked),
64/80/100-Pin Devices = Byte sum of (CW1 & 0x7DDF + CW2 & 0x87E3)
28/44-Pin Devices = Byte sum of (CW1 & 0x7FDF + CW2 & 0xFFF7)
Read Code
Protection
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
CFGB + SUM(0:0157FB)
0
CFGB + SUM(0:0157FB)
0
CFGB + SUM(0:0157FB)
0
Checksum Computation
Checksum
0xF8CC
0xF8CC
0xF8CC
Erased
0x0000
0x0000
0x0000
Value
© 2008 Microchip Technology Inc.
0xAAAAAA at 0x0 and Last
Checksum with
Code Address
0xF6CE
0xF6CE
0xF6CE
0x0000
0x0000
0x0000