PIC24FJ16GA002-E/ML Microchip Technology, PIC24FJ16GA002-E/ML Datasheet
PIC24FJ16GA002-E/ML
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PIC24FJ16GA002-E/ML Summary of contents
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... PIC24FJ16GA004 PIC24FJ64GA002 PIC24FJ48GA002 PIC24FJ32GA002 PIC24FJ16GA002 The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses in configuration Note 1: memory space. They are shown in hexadecimal in the format “DEVID DEVREV”. Refer to the “PIC24FJXXXGA0XX Flash Programming Specification” (DS39768) for detailed information 2: on Device and Revision IDs for your specific device ...
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... Write errors to ALCFGRPT register. In Slave mode, ACKSTAT bit state change. Issues with write operations on I2CxSTAT. IR baud clock only available during transmit. Issues with digital signal priorities with RP12 and RP18. No UERIF flag with multiple errors. (1) Affected Revisions A3/ 2010 Microchip Technology Inc. ...
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... A/D — 51. Converter Only those issues indicated in the last column apply to the current silicon revision. Note 1: 2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Issue Summary PERR and FERR not correctly set for all bytes in receive FIFO. Spontaneous BOR events with low-range V ...
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... Examples of this would be UART and SPI FIFO buffers, and the RTCVAL registers. The easiest way to ensure this does not occur is to execute a NOP instruction before entering Doze mode. Affected Silicon Revisions A3 2010 Microchip Technology Inc. ...
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... A3 Module: Core The PIC24FJ16GA002 and PIC24FJ16GA004 devices have 8K of data RAM implemented instead of 4K. This will cause the address error trap not to function for addresses between 2000h and 27FFh. Work around Do not access RAM beyond address 17FFh to maintain software compatibility with future device revisions ...
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... If a receive interrupt occurs, check the URXDA bit (UxSTA<0>) to ensure that valid data is available. On the first interrupt, no data will be present. The second interrupt will have the Sync field character (55h) in the receive FIFO. Affected Silicon Revisions A3 limits. If possible the auto-baud sequence can 2010 Microchip Technology Inc. ...
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... 2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 17. Module: Output Compare In PWM mode, the output compare module may miss a compare event when the current duty cycle register (OCxRS) value is 0x0000 (0% duty cycle) and the OCxRS register is updated with a value of 0x0001. The compare event is only missed the first time a value of 0x0001 is written to OCxRS and the PWM output remains low for one PWM period ...
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... When Slave Select mode is enabled, interrupting on SPIxSR empty and TX empty will occur at the same time. Therefore, interrupting on TX FIFO empty (SISEL<2:0> = 110) can be used as an alternative to interrupting when the Shift register is empty (SISEL<2:0> = 101). Affected Silicon Revisions A3 2010 Microchip Technology Inc. ...
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... All I/O Pins Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only Note 1: and are not tested. 2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY , meet the OH Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) -40° ...
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... ACKSTAT will be set at the end of a trans- mission and will remain set until receiving an ACK from the Master. Work around Store the value of the ACKSTAT bit immediately after receiving a NACK from the master. Affected Silicon Revisions A3 2010 Microchip Technology Inc. ...
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... Affected Silicon Revisions A3 2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 28. Module: I/O (Peripheral Pin Select) The remappable pin functions multiplexed to some pins do not have a higher priority than fixed digital signals assigned to those pins. By design, a remapped digital function should always have operation priority over any other fixed digital function on the same pin ...
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... MOV instruction is used to read the data at location, 8000h. Work around Do not use the first location of the a PSV page (address 8000h). The MPLAB C Compiler (v3.11 or later) supports the option, -merrata=psv_trap, to prevent it from generating code that would cause this erratum. Affected Silicon Revisions A3 2010 Microchip Technology Inc. ...
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... A4 X EXAMPLE 1: CHECKING THE STATE OF SPIxIF AGAINST THE SPI CLOCK while(IFS0bits.SPI1IF == 0){} while(PORTDbits.RD1 == 1){} SPI1BUF = 0xFF; 2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 2 36. Module (Master Mode) Under certain circumstances, a module operating in Master mode may Acknowledge its own com- mand addressed to a slave device. This happens when the following occurs: • ...
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... IVT and AIVT area of program space beyond the affected region. Map the addresses in the old vector tables to the new tables. These new tables can then be modified as needed to the actual addresses of the ISRs. Affected Silicon Revisions A3 secondary oscillator option 2010 Microchip Technology Inc. ...
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... Affected Silicon Revisions A3 2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 45. Module: Core Operations that immediately follow any manipula- tions of the DOZE<2:0> or DOZEN bits (CLKDIV<14:11>) may not execute properly. In particular, for instructions that operate on an SFR, data may not be read properly. Also, bits automatically cleared in hardware may not be cleared if the operation occurs during this interval ...
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... Users should consider the effect on I/O ports and other digital peripherals on those ports when ADC1MD is used for power conservation. Affected Silicon Revisions A3 2010 Microchip Technology Inc. data SRAM is enabled ...
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... Panasonic ECJ-3YX1C106K Panasonic ECJ-4YB1C106K Murata GRM32DR71C106KA01L Murata GRM31CR61C106KC31L 2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY When the regulator is enabled, a low-ESR (< 5Ω) capacitor is required on the V stabilize the voltage regulator output voltage. The V V pin must not be connected to V DDCORE use a capacitor of 10 µF connected to ground. The type can be ceramic or tantalum ...
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... For example, choose a ceramic capacitor rated at 16V for the 2.5V core voltage. Suggested capacitors are shown in Table 2-1. 2010 Microchip Technology Inc ...
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... Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only Note 1: and are not tested. This is the limit to which 2010 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 27-3. The Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature-40°C < -40° ...
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... Rev E Document (9/2010) Added silicon issue 51 (A/D Converter), added data sheet clarification issues 1 (Guidelines For Getting Started with 16-Bit Microcontrollers) and 2 ( Characteristics). Removed Table 27-10 because Table 27-3, a newer version, has been added. 2010 Microchip Technology Inc – Slave Electrical ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 2010 Microchip Technology Inc. 08/04/10 ...