PIC18F26J11-I/SS Microchip Technology, PIC18F26J11-I/SS Datasheet - Page 93

IC PIC MCU FLASH 64K 2V 28-SSOP

PIC18F26J11-I/SS

Manufacturer Part Number
PIC18F26J11-I/SS
Description
IC PIC MCU FLASH 64K 2V 28-SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets

Specifications of PIC18F26J11-I/SS

Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC18
No. Of I/o's
16
Ram Memory Size
3.6875KB
Cpu Speed
48MHz
No. Of Timers
2
Interface
EUSART, I2C, SPI
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, MA180023, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Package
28SSOP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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5.6.1
Enabling the PIC18 extended instruction set changes
the behavior of Indirect Addressing using the FSR2
register pair and its associated file operands. Under
proper conditions, instructions that use the Access
Bank, that is, most bit and byte-oriented instructions,
can invoke a form of Indexed Addressing using an
offset specified in the instruction. This special address-
ing mode is known as Indexed Addressing with Literal
Offset, or Indexed Literal Offset mode.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0);
• The file address argument is less than or equal to
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in Direct Addressing) or as
an 8-bit address in the Access Bank. Instead, the value
is interpreted as an offset value to an Address Pointer
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
© 2009 Microchip Technology Inc.
and
5Fh.
INDEXED ADDRESSING WITH
LITERAL OFFSET
PIC18F46J11 FAMILY
5.6.2
Any of the core PIC18 instructions that can use Direct
Addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all byte
and bit-oriented instructions, or almost one-half of the
standard PIC18 instruction set. Instructions that only
use Inherent or Literal Addressing modes are
unaffected.
Additionally, byte and bit-oriented instructions are not
affected if they use the Access Bank (Access RAM bit is
‘1’) or include a file address of 60h or above. Instructions
meeting these criteria will continue to execute as before.
A comparison of the different possible addressing
modes when the extended instruction set is enabled is
provided in Figure 5-9.
Those who desire to use byte or bit-oriented instruc-
tions in the Indexed Literal Offset mode should note the
changes to assembler syntax for this mode. This is
described in more detail in Section 26.2.1 “Extended
Instruction Syntax”.
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
DS39932C-page 93

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