PIC18LF44J11-I/ML Microchip Technology, PIC18LF44J11-I/ML Datasheet - Page 3
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PIC18LF44J11-I/ML
Manufacturer Part Number
PIC18LF44J11-I/ML
Description
IC PIC MCU FLASH 16K 2V 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
4.PIC18F26J11-ISO.pdf
(28 pages)
Specifications of PIC18LF44J11-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
22
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180023
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Silicon Errata Issues
1. Module: Master Synchronous Serial Port
2010 Microchip Technology Inc.
Note:
In Master I
occurs in the middle of an address or data
reception, the SCL clock stream will continue
endlessly and the RCEN bit of the SSPCON2
register will remain set improperly. When a Start
condition occurs after the improper Stop condi-
tion, nine additional clocks will be generated
followed by the RCEN bit going low.
Work around
Use low-impedance pull-ups on the SDA line to
reduce the possibility of noise glitches that may
trigger an improper Stop event. Use a time-out
event timer to detect the unexpected Stop con-
dition, and subsequently, the stuck RCEN bit.
Clear the stuck RCEN bit by clearing the SSPEN
bit of SSPCON1.
Affected Silicon Revisions
A2
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (Rev. A4).
A4
X
2
C Receive mode, if a Stop condition
PIC18F46J11 FAMILY
2. Module: Master Synchronous Serial Port
When configured for I
module may not receive the correct data, in extremely
rare cases. This occurs only if the Serial Receive/
Transmit Buffer Register (SSPBUF) is not read after
the SSPIF interrupt (PIR1<3>) has occurred, but before
the first rising clock edge of the next byte being
received.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
• Each time the SSPxIF is set, read the
Affected Silicon Revisions
A2
clock stretching feature. This is done by setting
the SEN bit (SSPxCON2<0>).
SSPxBUF before the first rising clock edge of
the next byte being received.
X
A4
X
(MSSP)
2
C slave reception, enable the
2
C™ slave reception, the MSSP
DS80435H-page 3