PIC18LF44J11-I/ML Microchip Technology, PIC18LF44J11-I/ML Datasheet - Page 175

IC PIC MCU FLASH 16K 2V 44-QFN

PIC18LF44J11-I/ML

Manufacturer Part Number
PIC18LF44J11-I/ML
Description
IC PIC MCU FLASH 16K 2V 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18LF44J11-I/ML

Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
22
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180023
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
10.2.2
When chip select is active and a write strobe occurs
(PMCS = 1 and PMWR = 1), the data from PMD<7:0>
is captured into the lower PMDIN1L register. The
PMPIF and IBF flag bits are set when the write
ends.The timing for the control signals in Write mode is
displayed in Figure 10-3. The polarity of the control
signals are configurable.
FIGURE 10-3:
FIGURE 10-4:
© 2009 Microchip Technology Inc.
PMD<7:0>
PMD<7:0>
PMCS1
PMCS1
PMWR
PMWR
PMPIF
PMPIF
PMRD
PMRD
OBE
OBE
IBF
IBF
WRITE TO SLAVE PORT
PARALLEL SLAVE PORT WRITE WAVEFORMS
PARALLEL SLAVE PORT READ WAVEFORMS
PIC18F46J11 FAMILY
10.2.3
When chip select is active and a read strobe occurs
(PMCS = 1 and PMRD = 1), the data from the
PMDOUT1L register (PMDOUT1L<7:0>) is presented
onto PMD<7:0>. Figure 10-4 provides the timing for the
control signals in Read mode.
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READ FROM SLAVE PORT
Q4
Q4
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Q1
Q1
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Q2
Q2
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DS39932C-page 175
Q3
Q3
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Q4
Q4

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