PIC18LF44J50-I/PT Microchip Technology, PIC18LF44J50-I/PT Datasheet - Page 364
![IC PIC MCU FLASH 16K 2V 44-TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18LF44J50-I/PT
Manufacturer Part Number
PIC18LF44J50-I/PT
Description
IC PIC MCU FLASH 16K 2V 44-TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18LF44J50-I/PT
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
22
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180024
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF44J50-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F46J50 FAMILY
21.4.4
An endpoint is defined to have a ping-pong buffer when
it has two sets of BD entries: one set for an Even
transfer and one set for an Odd transfer. This allows the
CPU to process one BD while the SIE is processing the
other BD. Double-buffering BDs in this way allows for
maximum throughput to/from the USB.
The USB module supports four modes of operation:
• No ping-pong support
• Ping-pong buffer support for OUT Endpoint 0 only
• Ping-pong buffer support for all endpoints
• Ping-pong buffer support for all other Endpoints
The ping-pong buffer settings are configured using the
PPB<1:0> bits in the UCFG register.
The USB module keeps track of the Ping-Pong Pointer
individually for each endpoint. All pointers are initially
reset to the Even BD when the module is enabled. After
FIGURE 21-6:
DS39931C-page 364
400h
47Fh
4FFh
except Endpoint 0
Note:
Maximum Memory
Used: 128 bytes
Maximum BDs:
32 (BD0 to BD31)
PPB<1:0> = 00
No Ping-Pong
Data RAM
Available
Buffers
as
PING-PONG BUFFERING
Memory area not shown to scale.
EP0 OUT
Descriptor
EP0 IN
Descriptor
EP1 OUT
Descriptor
EP1 IN
Descriptor
EP15 IN
Descriptor
BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES
400h
483h
4FFh
Ping-Pong Buffer
PPB<1:0> = 01
Maximum Memory
Used: 132 bytes
Maximum BDs:
33 (BD0 to BD32)
on EP0 OUT
Data RAM
Available
as
EP0 OUT Even
Descriptor
EP0 OUT Odd
Descriptor
EP0 IN
Descriptor
EP1 OUT
Descriptor
EP1 IN
Descriptor
EP15 IN
Descriptor
4FFh
400h
Ping-Pong Buffers
PPB<1:0> = 10
Maximum Memory
Used: 256 bytes
Maximum BDs: 6
4 (BD0 to BD63)
on all EPs
the completion of a transaction (UOWN cleared by the
SIE), the pointer is toggled to the Odd BD. After the
completion of the next transaction, the pointer is
toggled back to the Even BD and so on.
The Even/Odd status of the last transaction is stored in
the PPBI bit of the USTAT register. The user can reset
all Ping-Pong Pointers to Even using the PPBRST bit.
Figure 21-6 shows the four different modes of
operation and how USB RAM is filled with the BDs.
BDs have a fixed relationship to a particular endpoint,
depending on the buffering configuration. Table 21-2
provides the mapping of BDs to endpoints. This
relationship also means that gaps may occur in the
BDT if endpoints are not enabled contiguously. This
theoretically means that the BDs for disabled endpoints
could be used as buffer space. In practice, users
should avoid using such spaces in the BDT unless a
method of validating BD addresses is implemented.
EP0 OUT Even
Descriptor
EP0 OUT Odd
Descriptor
EP0 IN Even
Descriptor
EP0 IN Odd
Descriptor
EP1 OUT Even
Descriptor
EP1 OUT Odd
Descriptor
EP1 IN Odd
Descriptor
EP15 IN Odd
Descriptor
EP1 IN Even
Descriptor
4F7h
4FFh
400h
© 2009 Microchip Technology Inc.
Ping-Pong Buffers
on all other EPs
PPB<1:0> = 11
Maximum Memory
Used: 248 bytes
Maximum BDs:
62 (BD0 to BD61)
except EP0
Data RAM
Available
as
EP0 OUT
Descriptor
EP0 IN
Descriptor
EP1 OUT Even
Descriptor
EP1 OUT Odd
Descriptor
EP1 IN Odd
Descriptor
EP15 IN Odd
Descriptor
EP1 IN Even
Descriptor
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