PIC24HJ12GP201-I/P Microchip Technology, PIC24HJ12GP201-I/P Datasheet - Page 54
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PIC24HJ12GP201-I/P
Manufacturer Part Number
PIC24HJ12GP201-I/P
Description
IC PIC MCU FLASH 4KX24 18DIP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(242 pages)
2.PIC24HJ12GP201-ISO.pdf
(8 pages)
3.PIC24HJ12GP201-ISO.pdf
(84 pages)
4.PIC24HJ12GP201-ISO.pdf
(12 pages)
5.PIC24HJ12GP201-IP.pdf
(234 pages)
Specifications of PIC24HJ12GP201-I/P
Program Memory Type
FLASH
Program Memory Size
12KB (4K x 24)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
13
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit or 6-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164337 - MODULE SOCKET FOR PM3 40DIP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ12GP201-ISO PDF datasheet #2
- PIC24HJ12GP201-ISO PDF datasheet #3
- PIC24HJ12GP201-ISO PDF datasheet #4
- PIC24HJ12GP201-IP PDF datasheet #5
- Current page: 54 of 242
- Download datasheet (4Mb)
PIC24HJ12GP201/202
6.2
A POR circuit ensures the device is reset from power-
on. The POR circuit is active until V
V
delay T
become stable.
The device supply voltage characteristics must meet
the
requirements to
Section 22.0 “Electrical Characteristics” for details.
The POR status (POR) bit in the Reset Control
(RCON<0>) register is set to indicate the Power-on
Reset.
FIGURE 6-3:
DS70282D-page 52
POR
SYSRST
SYSRST
SYSRST
specified
threshold and the delay T
POR
POR
V
V
V
DD
DD
DD
ensures the internal device bias circuits
starting
V
DD
generate
dips before PWRT expires
BROWN-OUT SITUATIONS
voltage
the
POR
POR.
has elapsed. The
and
DD
crosses the
rise
Refer
rate
Preliminary
to
T
BOR
+ T
T
T
PWRT
BOR
BOR
6.3
The on-chip regulator has a BOR circuit that resets the
device when the V
device operation. The BOR circuit keeps the device in
Reset until V
T
regulator output becomes stable.
The BOR status (BOR) bit in the Reset Control
(RCON<1>) register is set to indicate the Brown-out
Reset.
The device will not run at full speed after a BOR as the
V
operation. The PWRT provides power-up time delay
(T
stabilized at the appropriate levels for full-speed
operation before the SYSRST is released.
The power-up timer delay (T
the
(FPWRT<2:0>)
(FPOR<2:0>) register, which provides eight settings
(from 0 ms to 128 ms). Refer to Section 19.0 “Special
Features” for further details.
Figure 6-3 shows the typical brown-out scenarios. The
Reset delay (T
rises above the V
BOR
DD
+ T
PWRT
+ T
PWRT
should rise to acceptable levels for full-speed
PWRT
has elapsed. The delay T
Power-on
) to ensure that the system power supplies have
BOR and PWRT
DD
BOR
crosses V
BOR
bits
DD
+ T
Reset
is too low (V
trip point.
PWRT
in
© 2009 Microchip Technology Inc.
BOR
) is initiated each time V
the
V
V
PWRT
V
Timer
BOR
BOR
BOR
threshold and the delay
BOR
DD
POR
) is programmed by
ensures the voltage
< V
Value
BOR
Configuration
) for proper
Select
DD
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