PIC24FJ32GA002-I/SP Microchip Technology, PIC24FJ32GA002-I/SP Datasheet - Page 147
![IC PIC MCU FLASH 11KX24 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC24FJ32GA002-I/SP
Manufacturer Part Number
PIC24FJ32GA002-I/SP
Description
IC PIC MCU FLASH 11KX24 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ16GA002-ISS.pdf
(268 pages)
3.PIC24FJ16GA002-ISS.pdf
(22 pages)
4.PIC24FJ64GA002-ISS.pdf
(256 pages)
5.PIC24FJ64GA004-IML.pdf
(16 pages)
Specifications of PIC24FJ32GA002-I/SP
Program Memory Type
FLASH
Program Memory Size
32KB (11K x 24)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C/IrDA/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DM300027, DV164033, MA240013, AC164127, DM240002
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Controller Family/series
PIC24
No. Of I/o's
21
Ram Memory Size
8KB
Cpu Speed
32MHz
No. Of Timers
5
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164337 - MODULE SOCKET FOR PM3 40DIPDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24FJ32GA002-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
15.2
To compute the Baud Rate Generator reload value, use
Equation 15-1.
EQUATION 15-1:
15.3
The I2CxMSK register (Register 15-3) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit loca-
tion (= 1) in the I2CxMSK register causes the slave
TABLE 15-1:
© 2007 Microchip Technology Inc.
Legend: Shaded rows represent invalid reload values for a given F
Note 1:
Note 1: Based on T
Note:
2:
3:
4:
Required
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
400 kHz
System
Setting Baud Rate When
Operating as a Bus Master
Slave Address Masking
1 MHz
1 MHz
1 MHz
F
PLL are disabled.
SCL
Based on T
This is the closest value to 400 kHz for this value of F
F
I2CxBRG cannot have a value of less than 2.
To comply with I
acknowledged by the I
CY
or
F
I2CxBRG
= 2 MHz is the minimum input clock frequency to have F
SCL
I
2
C™ CLOCK RATES
=
COMPUTING BAUD RATE
RELOAD VALUE
CY
--------------------------------------------- -
2
CY
⋅
=
= T
(
= T
I2CxBRG
⎛
⎝
2
CY
------------------ -
2 F
C™ definition, the addresses in Table 15-2 on page 146 are reserved and will not be
F
CY
⋅
F
CY
/2, Doze mode and PLL are disabled.
CY
16 MHz
16 MHz
16 MHz
/2; Doze mode and
8 MHz
4 MHz
8 MHz
4 MHz
2 MHz
8 MHz
4 MHz
SCL
2
F
C peripheral operating in Slave mode.
CY
⎞
⎠
+
–
1
)
1
(1)
(1)
PIC24FJ64GA004 FAMILY
Preliminary
(Decimal)
79
39
19
19
9
4
2
7
3
1
I2CxBRG Value
module to respond whether the corresponding address
bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK
is set to ‘00100000’, the slave module will detect both
addresses, ‘0000000’ and ‘00100000’.
To enable address masking, the IPMI (Intelligent
Peripheral Management Interface) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
15.3.1
The I2C1 has limited peripheral pin select capability.
The SDA1/SCL1 pins have alternative multiplexing
based on the setting of the I2C1SEL bit. The default
pins are used when the bit is set.
CY
Note:
.
SCL
(Hexadecimal)
SCL
and F
PERIPHERAL PIN SELECT
LIMITATIONS
The I2C1SEL bit is a Configuration bit in
the Flash Configuration Word. It is not part
of the regular device Configuration regis-
ters.
Section 3.1.3
Words”.
= 1 MHz.
4F
27
13
13
9
4
2
7
3
1
CY
.
For
more
“Flash
333 kHz
information,
1 MHz
1 MHz
DS39881B-page 145
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
Actual
1 MHz
F
Configuration
SCL
(3)
(4)
(2)
see