PIC16C711-20/P Microchip Technology, PIC16C711-20/P Datasheet - Page 23
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PIC16C711-20/P
Manufacturer Part Number
PIC16C711-20/P
Description
IC MCU OTP 1KX14 A/D 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16C711-20/P
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
13
Program Memory Type
OTP
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 4x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
18-DIP (0.300", 7.62mm)
Controller Family/series
PIC16C
No. Of I/o's
13
Ram Memory Size
68Byte
Cpu Speed
20MHz
No. Of Timers
1
Processor Series
PIC16C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
68 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
13
Number Of Timers
1
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
0 C
On-chip Adc
4 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1059 - ADAPTER 18 ZIF BD W/18SO PLUGSDVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C711-20/P
Manufacturer:
MICROCHIP
Quantity:
1 000
Part Number:
PIC16C711-20/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
4.3
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any reset, the upper bits of the
PC will be cleared. Figure 4-14 shows the two situa-
tions for the loading of the PC. The upper example in
the figure shows how the PC is loaded on a write to
PCL (PCLATH<4:0>
figure shows how the PC is loaded during a CALL or
GOTO instruction (PCLATH<4:3>
FIGURE 4-14: LOADING OF PC IN
4.3.1
A computed GOTO is accomplished by adding an off-
set to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
PC
PC
1997 Microchip Technology Inc.
12
12 11 10
2
PCL and PCLATH
COMPUTED GOTO
5
PCH
PCLATH<4:3>
PCH
PCLATH
PCLATH<4:0>
8
PCLATH
8
DIFFERENT SITUATIONS
7
7
PCH). The lower example in the
PCL
PCL
11
8
PCH).
0
0
Instruction with
PCL as
Destination
ALU
GOTO, CALL
Opcode <10:0>
4.3.2
The PIC16CXX family has an 8 level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
4.4
The PIC16C71X devices ignore both paging bits
(PCLATH<4:3>, which are used to access program
memory when more than one page is available. The
use of PCLATH<4:3> as general purpose read/write
bits for the PIC16C71X is not recommended since this
may affect upward compatibility with future products.
Note 1: There are no status bits to indicate stack
Note 2: There are no instructions/mnemonics
STACK
Program Memory Paging
overflow or stack underflow conditions.
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN,
tions, or the vectoring to an interrupt
address.
RETLW, and RETFIE instruc-
PIC16C71X
DS30272A-page 23