DSPIC30F2011-20I/SO Microchip Technology, DSPIC30F2011-20I/SO Datasheet - Page 201
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DSPIC30F2011-20I/SO
Manufacturer Part Number
DSPIC30F2011-20I/SO
Description
IC DSPIC MCU/DSP 12K 18SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20ISO.pdf
(206 pages)
Specifications of DSPIC30F2011-20I/SO
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Core Frequency
40MHz
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
12
Flash Memory Size
12KB
Supply Voltage Range
2.5V To 5.5V
Operating Temperature Range
-40°C To +85°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC30F005 - MODULE SCKT DSPIC30F 18DIP/SOIC
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F201120ISO
INDEX
Numerics
12-bit Analog-to-Digital Converter (A/D) Module .............. 113
A
A/D .................................................................................... 113
AC Characteristics ............................................................ 160
AC Temperature and Voltage Specifications .................... 160
ADC
ADC Conversion Speeds .................................................. 116
Address Generator Units .................................................... 43
Alternate Vector Table ........................................................ 69
Analog-to-Digital Converter. See ADC.
Assembler
Automatic Clock Stretch.................................................... 100
B
Bandgap Start-up Time
Barrel Shifter ....................................................................... 27
Bit-Reversed Addressing .................................................... 46
Block Diagrams
© 2010 Microchip Technology Inc.
Aborting a Conversion .............................................. 115
ADCHS Register ....................................................... 113
ADCON1 Register..................................................... 113
ADCON2 Register..................................................... 113
ADCON3 Register..................................................... 113
ADCSSL Register ..................................................... 113
ADPCFG Register..................................................... 113
Configuring Analog Port Pins.............................. 60, 119
Connection Considerations....................................... 119
Conversion Operation ............................................... 114
Effects of a Reset...................................................... 118
Operation During CPU Idle Mode ............................. 118
Operation During CPU Sleep Mode.......................... 118
Output Formats ......................................................... 118
Power-Down Modes.................................................. 118
Programming the Sample Trigger............................. 115
Register Map............................................................. 121
Result Buffer ............................................................. 114
Sampling Requirements............................................ 117
Selecting the Conversion Sequence......................... 114
Load Conditions ........................................................ 160
Selecting the Conversion Clock ................................ 115
MPASM Assembler................................................... 146
During 10-bit Addressing (STREN = 1)..................... 100
During 7-bit Addressing (STREN = 1)....................... 100
Receive Mode ........................................................... 100
Transmit Mode .......................................................... 100
Requirements............................................................ 166
Timing Characteristics .............................................. 166
Example ...................................................................... 47
Implementation ........................................................... 46
Modifier Values Table ................................................. 47
Sequence Table (16-Entry)......................................... 47
12-bit ADC Functional............................................... 113
16-bit Timer1 Module .................................................. 73
16-bit Timer2............................................................... 79
16-bit Timer3............................................................... 79
32-bit Timer2/3............................................................ 78
DSP Engine ................................................................ 24
dsPIC30F2011 ............................................................ 12
dsPIC30F2012 ............................................................ 13
dsPIC30F3013 ............................................................ 15
External Power-on Reset Circuit............................... 131
dsPIC30F2011/2012/3012/3013
BOR Characteristics ......................................................... 158
BOR. See Brown-out Reset.
Brown-out Reset
C
C Compilers
CAN Module
CLKOUT and I/O Timing
Code Examples
Code Protection ................................................................ 123
Control Registers ................................................................ 50
Core Architecture
CPU Architecture Overview ................................................ 19
Customer Change Notification Service............................. 205
Customer Notification Service .......................................... 205
Customer Support............................................................. 205
D
Data Accumulators and Adder/Subtractor .......................... 25
Data Address Space........................................................... 35
Data EEPROM Memory...................................................... 55
I
Input Capture Mode.................................................... 83
Oscillator System...................................................... 125
Output Compare Mode ............................................... 87
Reset System ........................................................... 129
Shared Port Structure................................................. 59
SPI.............................................................................. 94
SPI Master/Slave Connection..................................... 95
UART Receiver......................................................... 106
UART Transmitter..................................................... 105
Characteristics.......................................................... 158
Timing Requirements ............................................... 165
MPLAB C18.............................................................. 146
I/O Timing Characteristics ........................................ 181
I/O Timing Requirements.......................................... 181
Characteristics.......................................................... 164
Requirements ........................................................... 164
Data EEPROM Block Erase ....................................... 56
Data EEPROM Block Write ........................................ 58
Data EEPROM Read.................................................. 55
Data EEPROM Word Erase ....................................... 56
Data EEPROM Word Write ........................................ 57
Erasing a Row of Program Memory ........................... 51
Initiating a Programming Sequence ........................... 52
Loading Write Latches................................................ 52
NVMADR .................................................................... 50
NVMADRU ................................................................. 50
NVMCON.................................................................... 50
NVMKEY .................................................................... 50
Overview..................................................................... 19
Data Space Write Saturation ...................................... 27
Overflow and Saturation ............................................. 25
Round Logic ............................................................... 26
Write-Back .................................................................. 26
Alignment.................................................................... 38
Alignment (Figure) ...................................................... 38
Effect of Invalid Memory Accesses (Table) ................ 38
MCU and DSP (MAC Class) Instructions Example .... 37
Memory Map......................................................... 35, 36
Near Data Space ........................................................ 39
Software Stack ........................................................... 39
Spaces........................................................................ 38
Width .......................................................................... 38
Erasing ....................................................................... 56
Erasing, Block............................................................. 56
2
C .............................................................................. 98
DS70139G-page 201