PIC16F88-I/P Microchip Technology, PIC16F88-I/P Datasheet - Page 310

• Manufacturer Part Number: PIC16F88-I/P
• Description: IC MCU FLASH 4KX14 EEPROM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F88-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: SSP/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PICmicro MID-RANGE MCU FAMILY
17.4.10
DS31017A-page 17-34
I
2
C Master Mode Repeated Start Condition Timing
A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and
the I
When the SCL pin is sampled low, the baud rate generator is loaded with the contents of
SSPADD<5:0>, and begins counting. The SDA pin is released (brought high) for one baud rate
generator count (T
SCL pin will be de-asserted (brought high). When SCL is sampled high the baud rate generator
is re-loaded with the contents of SSPADD<6:0> and begins counting. SDA and SCL must be
sampled high for one T
for one T
cally cleared, and the baud rate generator is not reloaded, leaving the SDA pin held low. As soon
as a start condition is detected on the SDA and SCL pins, the S bit (SSPSTAT<3>) will be set.
The SSPIF bit will not be set until the baud rate generator has timed-out.
Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit
address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are
transmitted and an ACK is received, the user may then transmit an additional eight bits of
address (10-bit mode) or eight bits of data (7-bit mode).
Note 1: If RSEN is programmed while any other event is in progress, it will not take effect.
Note 2: A bus collision during the Repeated Start condition occurs if:
2
C logic module is in the idle state. When the RSEN bit is set, the SCL pin is asserted low.
BRG
• SDA is sampled low when SCL goes from low to high.
• SCL goes low before SDA is asserted low. This may indicates that another
while SCL is high. Following this, the RSEN bit (SSPCON2<1>) will be automati-
master is attempting to transmit a data ‘1’.
BRG
). When the baud rate generator times out, if SDA is sampled high, the
BRG
. This action is then followed by assertion of the SDA pin (SDA = 0)
Preliminary
1997 Microchip Technology Inc.