PIC16F628-20I/SS Microchip Technology, PIC16F628-20I/SS Datasheet - Page 38
![IC MCU FLASH 2KX14 COMP 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F628-20I/SS
Manufacturer Part Number
PIC16F628-20I/SS
Description
IC MCU FLASH 2KX14 COMP 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC16F627-04P.pdf
(170 pages)
Specifications of PIC16F628-20I/SS
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Controller Family/series
PIC16F
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
224Byte
Cpu Speed
20MHz
No. Of Timers
3
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
224 B
Interface Type
SCI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
Data Converters
-
Lead Free Status / Rohs Status
Details
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PIC16F62X
FIGURE 5-10:
DS40300C-page 36
WR PORTB
WR TRISB
RD TRISB
RD PORTB
RBPU
Peripheral OE
USART Slave Clock In
PORT/PERIPHERAL Select
USART TX/CK Output
Data Bus
Note
1:
2:
Port/Peripheral select signal selects between port
data and peripheral output.
Peripheral OE (output enable) is only active if
peripheral select is active.
(2)
TRIS Latch
Data Latch
D
D
CK
CK
BLOCK DIAGRAM OF
RB2/TX/CK PIN
(1)
Q
Q
Q
Schmitt
Trigger
Q
Q
EN
0
1
D
TTL
Input
Buffer
V
P
DD
Weak
Pull-up
V
V
DD
SS
TX/CK
RB2/
Preliminary
FIGURE 5-11:
RBPU
PORT/PERIPHERAL Select
USART TX/CK output
Data Bus
WR PORTB
WR TRISB
Peripheral OE
RD TRISB
RD PORTB
USART Slave Clock In
Note
1:
2:
Port/Peripheral select signal selects between port
data and peripheral output.
Peripheral OE (output enable) is only active if
peripheral select is active.
(2)
TRIS Latch
Data Latch
D
D
CK
CK
BLOCK DIAGRAM OF
RB3/CCP1 PIN
(1)
2003 Microchip Technology Inc.
Q
Q
Schmitt
Q
Trigger
Q
Q
EN
0
1
D
TTL
Input
Buffer
V
P
DD
V
Weak
Pull-up
V
DD
SS
CCP1
RB3/
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