ATMEGA8535L-8JU Atmel, ATMEGA8535L-8JU Datasheet - Page 3

• Manufacturer Part Number: ATMEGA8535L-8JU
• Description: MCU AVR 8K ISP FLASH MEM 44-PLCC
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8535L-8JU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 512Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Overview
Block Diagram
2502KS–AVR–10/06
The ATmega8535 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing instructions in a single clock cycle, the
ATmega8535 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
Figure 2. Block Diagram
V
GND
AVCC
CC
AREF
PROGRAMMING
INSTRUCTION
INSTRUCTION
AVR CPU
CONTROL
PROGRAM
PROGRAM
COUNTER
REGISTER
DECODER
FLASH
LINES
PORTA DIGITAL INTERFACE
MUX &
LOGIC
PORTB DIGITAL INTERFACE
PORTA DRIVERS/BUFFERS
PORTB DRIVERS/BUFFERS
ADC
+
-
PA0 - PA7
PB0 - PB7
REGISTERS
INTERFACE
INTERFACE
GENERAL
PURPOSE
REGISTER
POINTER
STATUS
STACK
COMP.
SRAM
ALU
ADC
SPI
X
Y
Z
OSCILLATOR
WATCHDOG
COUNTERS
INTERRUPT
MCU CTRL.
INTERNAL
& TIMING
EEPROM
TIMERS/
USART
PORTC DIGITAL INTERFACE
TIMER
PORTD DIGITAL INTERFACE
PORTC DRIVERS/BUFFERS
PORTD DRIVERS/BUFFERS
UNIT
TWI
PC0 - PC7
PD0 - PD7
ATmega8535(L)
OSCILLATOR
OSCILLATOR
OSCILLATOR
CALIBRATED
INTERNAL
XTAL1
XTAL2
RESET
3