PIC16LF88-I/SO Microchip Technology, PIC16LF88-I/SO Datasheet - Page 3
![IC MCU FLASH 4KX14 EEPROM 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16LF88-I/SO
Manufacturer Part Number
PIC16LF88-I/SO
Description
IC MCU FLASH 4KX14 EEPROM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16F87-IP.pdf
(228 pages)
4.PIC16F87-IP.pdf
(8 pages)
5.PIC16F87-IP.pdf
(4 pages)
6.PIC16F87-IP.pdf
(8 pages)
7.PIC16F88-ISO.pdf
(214 pages)
Specifications of PIC16LF88-I/SO
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
18-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
SSP/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
Minimum Operating Temperature
- 40 C
On-chip Adc
7-ch x 10-bit
Package
18SOIC W
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF88-I/SO
Manufacturer:
MICROCHIP
Quantity:
3 000
Company:
Part Number:
PIC16LF88-I/SO
Manufacturer:
MICROCHIP
Quantity:
4 180
Change 3. Section 4.6.4
4.6.4
The IRCF bits can be modified at any time regardless of
which clock source is currently being used as the system
clock. The internal oscillator allows users to change the
frequency during run time. This is achieved by modifying
the IRCF bits in the OSCCON register. The sequence of
events that occur after the IRCF bits are modified is
dependent upon the initial value of the IRCF bits before
they are modified. If the INTRC (31.25 kHz, IRCF<2:0>
= 000) is running and the IRCF bits are modified to any
other value than ‘000’, the clock source is switched
immediately. The IOFS bit (OSCCON<2>) becomes set
approximately 100 μs later. Code execution continues
while the new frequency stabilizes. Time sensitive code
should wait for the IOFS bit to become set before
continuing. This bit can be monitored to ensure that the
frequency is stable before using the system clock in time
critical applications.
TABLE 4-3:
© 2008 Microchip Technology Inc.
Note 1:
INTRC/Sleep
(31.25 kHz)
(31.25 kHz)
Sleep/POR
Section 4.6.4 “Modifying the IRCF Bits” is
changed as shown.
INTRC
INTRC
From
Sleep
2:
Clock Switch
The 5-10 μs start-up delay is based on a 1 MHz system clock.
The INTOSC clock source is available immediately and clocks the controller. 100 μs after the INTOSC is
enabled (when IOFS becomes set), the INTOSC frequency is stable and meets specifications.
MODIFYING THE IRCF BITS
LP, XT, HS 32.768 kHz-20 MHz
Postscaler
Postscaler
INTOSC/
INTOSC/
INTOSC
INTOSC
OSCILLATOR DELAY EXAMPLES
T1OSC
EC, RC
EC, RC
INTRC
To
125 kHz-8 MHz
125 kHz-8 MHz
DC – 20 MHz
DC – 20 MHz
Frequency
32.768 kHz
31.25 kHz
1024 Clock Cycles
Oscillator Delay
CPU Start-up
CPU Start-up
100 μs
100 μs
(OST)
(2)
If the IRCF bits are modified while the internal oscillator
is running at any other frequency than INTRC
(31.25 kHz, IRCF<2:0>
switched immediately and IOFS remains set.
Change 4. Section 4.6.5
4.
Change 5. Table 4-3
(2)
and
The fourth step of the first of three switching
sequences in Section 4.6.5 “Clock Transition
Sequence” is changed as shown.
The IOFS bit is clear to indicate that the clock is
unstable. In approximately 100 μs, the IOFS bit
will become set, indicating INTOSC is stable.
Code execution continues while IOFS is clear.
Time dependent code should wait for IOFS to
become set before continuing.
Table 4-3
indicating new or modified text.
(1)
(1)
Following a wake-up from Sleep mode or
POR, CPU start-up is invoked to allow the
CPU to become ready for code execution.
Following a change from INTRC, an OST
of 1024 cycles must occur.
Refer to Section 4.6.4 “Modifying the
IRCF Bits” for further details.
is changed as shown, with change bars
PIC16F87/88
≠
Comments
000), the clock source is
DS80365A-page 3