PIC16LF872-I/SP Microchip Technology, PIC16LF872-I/SP Datasheet - Page 137

• Manufacturer Part Number: PIC16LF872-I/SP
• Description: IC MCU FLASH 2KX14 EE A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF872-I/SP

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Oscillator Type: External
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16LF
• No. Of I/o's: 22
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• No.: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 14-15:
TABLE 14-8:
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
2002 Microchip Technology Inc.
Param
No.
100
101
102
103
106
107
109
110
90
91
92
2: A fast mode (400 kHz) I
Note: Refer to Figure 14-3 for load conditions.
SDA
Out
SDA
In
SCL
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
that T
of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line:
T
released.
T
T
T
T
T
T
T
T
T
T
T
C
R
SU
SU
SU
AA
HIGH
LOW
R
F
HD
HD
BUF
B
Sym
max.+ T
:
:
:
:
:
STA
DAT
STO
SU
STA
DAT
:
I
DAT
2
C BUS DATA REQUIREMENTS
Clock High Time
Clock Low Time
SDA and SCL Rise
Time
SDA and SCL Fall
Time
START Condition
Setup Time
START Condition Hold
Time
Data Input Hold Time
Data Input Setup Time 100 kHz mode
STOP Condition
Setup Time
Output Valid From
Clock
Bus Free Time
Bus Capacitive Loading
SU
I
:
DAT
2
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period
90
C BUS DATA TIMING
103
= 1000 + 250 = 1250 ns (according to the standard mode I
91
2
C bus device can be used in a standard mode (100 kHz) I
Characteristic
109
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100
106
101
109
20 + 0.1C
20 + 0.1C
1.5T
1.5T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
CY
CY
107
B
B
1000
3500
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
C bus specification) before the SCL line is
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
s
s
s
s
s
s
s
s
s
s
s
s
s
2
C bus system, but the requirement
Device must operate at a mini-
mum of 1.5 MHz
Device must operate at a mini-
mum of 10 MHz
Device must operate at a mini-
mum of 1.5 MHz
Device must operate at a mini-
mum of 10 MHz
C
10 to 400 pF
C
10 to 400 pF
Only relevant for Repeated
START condition
After this period, the first clock
pulse is generated
(Note 2)
(Note 1)
Time the bus must be free before
a new transmission can start
PIC16F872
B
B
92
is specified to be from
is specified to be from
102
Conditions
110
DS30221B-page 135