PIC18LF27J13-I/SS Microchip Technology, PIC18LF27J13-I/SS Datasheet - Page 8

• Manufacturer Part Number: PIC18LF27J13-I/SS
• Description: IC PIC MCU 128KB FLASH 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF27J13-I/SS

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 1.8V To 3.6V
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2XJXX/4XJXX FAMILY
FIGURE 2-7:
2.5
The PGC pin is used as a clock input pin and the PGD
pin is used for entering command bits and data
input/output during serial operation. Commands and
data are transmitted on the rising edge of PGC, latched
on the falling edge of PGC and are Least Significant bit
(LSb) first.
2.5.1
All instructions are 20 bits, consisting of a leading 4-bit
command followed by a 16-bit operand, which depends
on the type of command being executed. To input a
command, PGC is cycled four times. The commands
needed for programming and verification are shown in
Table 2-3.
Depending on the 4-bit command, the 16-bit operand
represents 16 bits of input data or 8 bits of input data
and 8 bits of output data.
FIGURE 2-8:
DS39687E-page 8
PGC
PGD
MCLR
V
PGD
PGC
DD
Serial Program/Verify Operation
FOUR-BIT COMMANDS
P3
4-Bit Command
1
P2
1
2
PGD = Input
P4
0
EXITING
PROGRAM/VERIFY MODE
TABLE WRITE, POST-INCREMENT TIMING (1101)
3
1
V
P16
4
1
IH
P2A
P5
P2B
P17
V
1
0
IH
2
0
0
3
0
4
0
5
0
6
PGD = Input
0
16-Bit Data Payload
4
7
1
8
0
command/operand to the device.
Throughout this specification, commands and data are
presented as illustrated in Table 2-4. The 4-bit command
is shown Most Significant bit (MSb) first. The command
operand, or “Data Payload”, is shown <MSB><LSB>.
Figure 2-8 demonstrates how to serially present a 20-bit
2.5.2
The core instruction passes a 16-bit instruction to the
CPU core for execution. This is needed to set up
registers as appropriate for use with other commands.
TABLE 2-3:
TABLE 2-4:
Core Instruction
(Shift in 16-bit instruction)
Shift out TABLAT register
Table Read
Table Read, Post-Increment
Table Read, Post-Decrement
Table Read, Pre-Increment
Table Write
Table Write, Post-Increment by 2
Table Write, Start Programming,
Post-Increment by 2
Table Write, Start Programming
9
Command
0
10
1101
4-Bit
0
C
11
1
12
CORE INSTRUCTION
1
Description
Payload
13
3C 40
1
Data
14
COMMANDS FOR
PROGRAMMING
SAMPLE COMMAND
SEQUENCE
1
3
15
0
© 2009 Microchip Technology Inc.
Table Write,
post-increment by 2
16
0
P5A
Fetch Next 4-Bit Command
Core Instruction
1
n
2
n
3
n
Command
4
0000
0010
1000
1001
1010
1011
1100
1101
1110
1111
4-Bit
n