PIC18F66J16-I/PT Microchip Technology, PIC18F66J16-I/PT Datasheet - Page 43

• Manufacturer Part Number: PIC18F66J16-I/PT
• Description: IC PIC MCU FLASH 48KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F66J16-I/PT

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 52
• Program Memory Type: FLASH
• Ram Size: 3930 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 52
• Ram Memory Size: 3930Byte
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162091 - HEADER MPLAB ICD2 18F87J11 64/80MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.0
The PIC18F87J11 Family of devices provides the ability
to manage power consumption by simply managing
clocking to the CPU and the peripherals. In general, a
lower clock frequency and a reduction in the number of
circuits being clocked constitutes lower consumed
power. For the sake of managing power in an
application, there are three primary modes of operation:
• Run mode
• Idle mode
• Sleep mode
These modes define which portions of the device are
clocked and at what speed. The Run and Idle modes
may use any of the three available clock sources (pri-
mary, secondary or internal oscillator block); the Sleep
mode does not use a clock source.
The
power-saving features offered on previous devices.
One is the clock switching feature, offered in other
PIC18 devices, allowing the controller to use the
Timer1 oscillator in place of the primary oscillator. Also
included is the Sleep mode, offered by all PIC
devices, where all device clocks are stopped.
3.1
Selecting a power-managed mode requires two
decisions: if the CPU is to be clocked or not and which
clock source is to be used. The IDLEN bit
(OSCCON<7>) controls CPU clocking, while the
SCS1:SCS0 bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock
sources and affected modules are summarized in
Table 3-1.
TABLE 3-1:
© 2009 Microchip Technology Inc.
Sleep
PRI_RUN
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
Note 1:
Mode
2:
power-managed
POWER-MANAGED MODES
Selecting Power-Managed Modes
IDLEN reflects its value when the SLEEP instruction is executed.
Includes INTRC and INTOSC postcaler (internal oscillator block).
IDLEN
POWER-MANAGED MODES
N/A
N/A
N/A
0
1
1
1
OSCCON<7,1:0>
(1)
modes
SCS1:SCS0
N/A
10
10
01
11
01
11
include
several
Clocked
Clocked
Clocked
Module Clocking
CPU
Off
Off
Off
Off
®
Peripherals
Clocked
Clocked
Clocked
Clocked
Clocked
Clocked
Off
PIC18F87J11 FAMILY
3.1.1
The SCS1:SCS0 bits allow the selection of one of three
clock sources for power-managed modes. They are:
• the primary clock, as defined by the
• the secondary clock (Timer1 oscillator)
• the internal oscillator
3.1.2
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS1:SCS0 bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 3.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator
select bits, or changing the IDLEN bit, prior to issuing a
SLEEP instruction. If the IDLEN bit is already
configured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.
FOSC2:FOSC0 Configuration bits
None – All clocks are disabled
Primary – HS, EC, HSPLL, ECPLL, INTOSC
oscillator;
this is the normal, full-power execution mode
Secondary – Timer1 oscillator
Internal oscillator block
Primary – HS, EC, HSPLL, ECPLL, INTOSC
Secondary – Timer1 oscillator
Internal oscillator block
Available Clock and Oscillator Source
CLOCK SOURCES
ENTERING POWER-MANAGED
MODES
(2)
(2)
DS39778D-page 43