PIC18LF2321-I/ML Microchip Technology, PIC18LF2321-I/ML Datasheet - Page 3
![IC PIC MCU FLASH 4KX16 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18LF2321-I/ML
Manufacturer Part Number
PIC18LF2321-I/ML
Description
IC PIC MCU FLASH 4KX16 28QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(402 pages)
3.PIC18F2221-ISO.pdf
(8 pages)
4.PIC18F2221-ISO.pdf
(30 pages)
5.PIC18F2221-ISO.pdf
(46 pages)
Specifications of PIC18LF2321-I/ML
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Silicon Errata Issues
1. Module: 10-Bit Analog-to-Digital
2010 Microchip Technology Inc.
Note:
When the AD clock source is selected as 2 T
or RC (when ADCS<2:0 = 000 or x11), in
extremely rare cases, the E
Error) and E
exceed
codes 511 and 512.
Work around
Select the AD clock source as 4 T
16 T
selecting 2 T
Affected Silicon Revisions
B2
X
OSC
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B3).
B3
, 32 T
X
the
Converter (A/D)
DL
OSC
(Differential Linearity Error) may
OSC
data
or RC.
or 64 T
sheet
IL
(Integral Linearity
OSC
specification
OSC
and avoid
, 8 T
PIC18F2221/2321/4221/4321
OSC
OSC
at
,
2. Module: Master Synchronous Serial Port
When configured for I
MSSP module may not receive the correct data, in
extremely rare cases. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPBUF) is
not read within a window after the SSPIF interrupt
(PIR1<3>) has occurred.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
• Each time the SSPIF is set, read the SSPBUF
Affected Silicon Revisions
B2
clock stretching feature.
This
(SSPCON2<0>).
before the first rising clock edge of the next byte
being received.
X
B3
X
is
(MSSP)
done
2
C slave reception, enable the
by
2
C™ slave reception, the
setting
DS80285C-page 3
the
SEN
bit