PIC24FJ64GA002-I/SS Microchip Technology, PIC24FJ64GA002-I/SS Datasheet - Page 4

• Manufacturer Part Number: PIC24FJ64GA002-I/SS
• Description: IC PIC MCU FLASH 64K 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA002-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DV164033, MA240013, AC164127, DM240002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Controller Family/series: PIC24
• No. Of I/o's: 21
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164338 - MOD SKT PIC24F/DSPIC33F 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ64GA004 FAMILY
Silicon Errata Issues
1. Module: JTAG
2. Module: Low-Voltage Detect
DS80470E-page 4
Note:
When the JTAG is disabled, the pull-up resistor on
the TDI pin (pin 35/RA9) will stay enabled on the
44-pin variants of the device. This can cause the
device to draw extra current when asleep if the pin
is used as an input and held low.
Work around:
The pin will not draw extra current if any of the
following work around techniques are used:
• The pin is used as an output.
• The pin is driven high as an input.
• JTAG is enabled.
Affected Silicon Revisions
The Low-Voltage Detect interrupt will not occur if
the device comes out of Reset in a low-voltage
state. To trigger an interrupt, the voltage must
decrease to a low-voltage range while the device
is running.
Work around
None.
Affected Silicon Revisions
A3/
A3/
A4
A4
X
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B8).
B4
B4
B5
B5
B8
B8
3. Module: Core
4. Module: Core
If a clock failure occurs when the device is in Idle
mode, the oscillator failure trap does not vector to
the Trap Service Routine. Instead, the device will
simply wake-up from Idle mode and continue code
execution if the Fail-Safe Clock Monitor (FSCM) is
enabled.
Work around
Whenever the device wakes up from Idle (assuming
the FSCM is enabled), the user software should
check the status of the OSCFAIL bit (INTCON1<1>)
to determine whether a clock failure occurred, and
then perform an appropriate clock switch operation.
Affected Silicon Revisions
If a RAM read is performed on the instruction
immediately prior to enabling Doze mode, then an
extra read event will occur when Doze mode is
enabled. On most SFRs and on user RAM space,
this will have no visible effect. However, this can
cause registers which perform actions on reads,
such as auto-incrementing or decrementing a
pointer or removing data from a FIFO buffer, to
repeat that action, possibly resulting in lost data.
Work around
On the instruction prior to entering Doze mode, be
sure not to read a register which performs a sec-
ondary action. Examples of this would be UART
and SPI FIFO buffers, and the RTCVAL registers.
The easiest way to ensure this does not occur is to
execute a NOP instruction before entering Doze
mode.
Affected Silicon Revisions
A3/
A3/
A4
A4
X
X
B4
B4
B5
B5
 2010 Microchip Technology Inc.
B8
B8