PIC18F27J13-I/SO Microchip Technology, PIC18F27J13-I/SO Datasheet - Page 4

• Manufacturer Part Number: PIC18F27J13-I/SO
• Description: IC PIC MCU 128KB FLASH 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J13-I/SO

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Digital Ic Case Style: SOIC
• Supply Voltage Range: 1.8V To 5.5V
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 8
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DM164128, DM180021, DM183026-2, DV164131, MA180030, DM183022, DM183032, DV164136, MA180024
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F47J13 FAMILY
4. Module: Master Synchronous Serial Port
5. Module: Master Synchronous Serial Port
When configured for I
module may not receive the correct data, in extremely
rare cases. This occurs only if the Serial Receive/
Transmit Buffer register (SSPxBUF) is not read after
the SSP1IF interrupt (PIR1<3>) has occurred, but
before the first rising clock edge of the next byte being
received.
EXAMPLE 1:
DS80503D-page 4
;Initial conditions: SPEN = 0 (module disabled)
;To re-enable the module:
;Re-Initialize TXSTAx, BAUDCONx, SPBRGx, SPBRGHx registers (if needed)
;Re-Initialize RCSTAx register (if needed), but do not set SPEN = 1 yet
;Now enable the module, but add a 2-Tcy delay before executing any two-cycle
;instructions
bsf
nop
nop
In Master I
occurs in the middle of an address or data
reception, the SCL clock stream will continue
endlessly and the RCEN bit of the SSPxCON2
register will remain set improperly. When a Start
condition occurs after the improper Stop condi-
tion, nine additional clocks will be generated
followed by the RCEN bit going low.
Work around
Use low-impedance pull-ups on the SDA line to
reduce the possibility of noise glitches that may
trigger an improper Stop event. Use a time-out
event timer to detect the unexpected Stop con-
dition, and subsequently, the stuck RCEN bit.
Clear the stuck RCEN bit by clearing the SSPEN
bit of SSPxCON1.
Affected Silicon Revisions
A1
X
RCSTA1, SPEN
2
(MSSP)
C Receive mode, if a Stop condition
RE-ENABLING A EUSART MODULE
2
C™ slave reception, the MSSP
;or RCSTA2 if EUSART2
;1 Tcy delay
;1 Tcy delay (two total)
6. Module: Enhanced Universal
Work around
The issue can be resolved in either of these ways:
• Prior to the I
• Each time the SSPxIF is set, read the
Affected Silicon Revisions
In rare situations, when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (SPEN bit
• The EUSART is re-enabled (RCSTAx<7> = 1)
• A two-cycle instruction is executed immediately
Work around
Add a 2 T
enables the EUSART module (sets SPEN, CREN
or TXEN = 1).
See
Affected Silicon Revisions
A1
A1
clock stretching feature. This is done by setting
the SEN bit (SSPxCON2<0>).
SSPxBUF before the first rising clock edge of
the next byte being received.
X
(RCSTAx<7>) = 0)
after setting SPEN, CREN or TXEN = 1
X
Example
CY
Synchronous Asynchronous
Receiver Transmitter (EUSART)
delay after any instruction that re-
1.
2
C slave reception, enable the
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