PIC16LF872-I/SS Microchip Technology, PIC16LF872-I/SS Datasheet - Page 65
![IC MCU FLASH 2KX14 EE A/D 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16LF872-I/SS
Manufacturer Part Number
PIC16LF872-I/SS
Description
IC MCU FLASH 2KX14 EE A/D 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16C770-ISO.pdf
(8 pages)
2.PIC16F872-ISO.pdf
(168 pages)
3.PIC16F872-ISO.pdf
(5 pages)
4.PIC16F872-ISO.pdf
(6 pages)
Specifications of PIC16LF872-I/SS
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC16LF
No. Of I/o's
22
Eeprom Memory Size
64Byte
Ram Memory Size
128Byte
Cpu Speed
20MHz
No. Of Timers
3
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C, SPI, SSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
22
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF872-I/SS
Manufacturer:
AD
Quantity:
1 560
Part Number:
PIC16LF872-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
9.2.5
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET or when the MSSP module is
disabled. Control of the I
P bit is set, or the bus is IDLE, with both the S and P
bits clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
FIGURE 9-9:
9.2.6
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the MSSP module is disabled. Control of the I
bus may be taken when bit P (SSPSTAT<4>) is set, or
the bus is IDLE with both the S and P bits clear. When
the bus is busy, enabling the SSP interrupt will gener-
ate the interrupt when the STOP condition occurs.
In Multi-Master operation, the SDA line must be moni-
tored for arbitration to see if the signal level is the
expected output level. This check is performed in hard-
ware, with the result placed in the BCLIF bit.
© 2006 Microchip Technology Inc.
SDA
SCL
MASTER MODE
MULTI-MASTER MODE
SSP BLOCK DIAGRAM (I
2
C bus may be taken when the
SDA In
SCL In
Bus Collision
Read
MSb
START bit, STOP bit,
Write Collision Detect
End of XMIT/RCV
START bit Detect,
State Counter for
Clock Arbitration
STOP bit Detect
Acknowledge
SSPBUF
SSPSR
Generate
2
2
C
C MASTER MODE)
LSb
Write
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (an SSP Interrupt will occur if
enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated START
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A START Condition
• A Repeated START Condition
• An Acknowledge Condition
Clock
Data Bus
Shift
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
PIC16F872
SSPADD<6:0>
SSPM3:SSPM0,
Baud
Rate
Generator
DS30221C-page 63