PIC18LF1330-I/P Microchip Technology, PIC18LF1330-I/P Datasheet - Page 131
![IC PIC MCU FLASH 4KX16 18DIP](/photos/6/76/67657/18-dip_300mil__sml.jpg)
PIC18LF1330-I/P
Manufacturer Part Number
PIC18LF1330-I/P
Description
IC PIC MCU FLASH 4KX16 18DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1230-ISO.pdf
(6 pages)
4.PIC18F1230-ISO.pdf
(12 pages)
5.PIC18F1230-ISO.pdf
(4 pages)
Specifications of PIC18LF1330-I/P
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
256Byte
Cpu Speed
40MHz
No. Of Timers
2
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF1330-I/P
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC18LF1330-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- AC162078 PDF datasheet #2
- PIC18F1230-ISO PDF datasheet #3
- PIC18F1230-ISO PDF datasheet #4
- PIC18F1230-ISO PDF datasheet #5
- Current page: 131 of 318
- Download datasheet (3Mb)
14.6
PWM duty cycle is defined by the PDCx (PDCxL and
PDCxH) registers. There are a total of three PWM Duty
Cycle registers for four pairs of PWM channels. The
Duty Cycle registers have 14-bit resolution by combin-
ing the six LSbs of PDCxH with the 8 bits of PDCxL.
PDCx is a double-buffered register used to set the
counting period for the PWM time base.
14.6.1
There are three 14-bit Special Function Registers used
to specify duty cycle values for the PWM module:
• PDC0 (PDC0L and PDC0H)
• PDC1 (PDC1L and PDC1H)
• PDC2 (PDC2L and PDC2H)
The value in each Duty Cycle register determines the
amount of time that the PWM output is in the active
state. The upper 12 bits of PDCx hold the actual duty
cycle value from PTMRH/L<11:0>, while the lower two
bits control which internal Q clock the duty cycle match
will occur. This 2-bit value is decoded from the Q
clocks, as shown in Figure 14-11, when the prescaler is
1:1 (PTCKPS<1:0> = 00).
In Edge-Aligned mode, the PWM period starts at Q1 and
ends when the Duty Cycle register matches the PTMR
register as follows. The duty cycle match is considered
when the upper 12 bits of the PDCx are equal to the
FIGURE 14-11:
2009 Microchip Technology Inc.
Note 1: This value is decoded from the Q clocks:
PTMR<11:0>
PDCx<13:0>
PWM Duty Cycle
PWM DUTY CYCLE REGISTERS
00 = duty cycle match occurs on Q1
01 = duty cycle match occurs on Q2
10 = duty cycle match occurs on Q3
11 = duty cycle match occurs on Q4
DUTY CYCLE COMPARISON
Unused
Unused
PTMRH<7:0>
PTMRH<3:0>
PDCxH<7:0>
PDCxH<5:0>
PTMR and the lower 2 bits are equal to Q1, Q2, Q3 or
Q4, depending on the lower two bits of the PDCx (when
the prescaler is 1:1 or PTCKPS<1:0> = 00)
Each compare unit has logic that allows override of the
PWM signals. This logic also ensures that the PWM
signals will complement each other (with dead-time
insertion) in Complementary mode (see Section 14.7
“Dead-Time Generators”).
Note:
Note:
Comparator
PIC18F1230/1330
PTMRL<7:0>
PTMRL<7:0>
When
(PTCKPS<1:0> ~00), the duty cycle
match occurs at the Q1 clock of the
instruction cycle when the PTMR and
PDCx match occurs.
To get the correct PWM duty cycle, always
multiply the calculated PWM duty cycle
value by four before writing it to the PWM
Duty Cycle registers. This is due to the two
additional LSBs in the PWM Duty Cycle
registers which are compared against the
internal Q clock for the PWM duty cycle
match.
the
PDCxL<7:0>
PDCxL<7:0>
prescaler
DS39758D-page 131
is
Q Clocks
.
<1:0>
not
(1)
1:1
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