PIC18F87J10-I/PT Microchip Technology, PIC18F87J10-I/PT Datasheet

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PIC18F87J10-I/PT

Manufacturer Part Number
PIC18F87J10-I/PT
Description
IC PIC MCU FLASH 64KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F87J10-I/PT

Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
66
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 15x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI/I2C/MSSP/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
66
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DV164136, DM183032, DM164120-5
Minimum Operating Temperature
- 40 C
On-chip Adc
15-ch x 10-bit
Package
80TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164328 - MODULE SKT FOR 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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The PIC18F87J10 family parts you have received
conform functionally to the Device Data Sheet
(DS39663D), except for the anomalies described
below. Any Data Sheet Clarification issues related to
the PIC18F87J10 family will be reported in a separate
Data Sheet errata. Please check the Microchip web site
for any existing issues.
The
PIC18F87J10 family devices with these Device/
Revision IDs:
1. Module: Flash Program Memory
© 2007 Microchip Technology Inc.
The Device IDs (DEVID1 and DEVID2) are located at
addresses
configuration space. They are shown in hexadecimal
in the format “DEVID2 DEVID1”.
Part Number
PIC18F65J10
PIC18F65J15
PIC18F66J10
PIC18F66J15
PIC18F67J10
PIC18F85J10
PIC18F85J15
PIC18F86J10
PIC18F86J15
PIC18F87J10
Writes to program memory address 300000h, that
are not blocked, can cause the program memory
at different locations to be corrupted.
Work around
Do not write to address 300000h. If you wish to
modify the contents of the Configuration registers,
then modify the Configuration Words located at the
end of the user memory and issue a Reset com-
mand. This will reload the Configuration registers
with the new configuration setting.
The end of the user memory is:
• PIC18FX5J10 devices — 7FF4h
• PIC18FX5J10 devices — 3FF4h
For additional information, see the Device Data
Sheet (DS39663), Section 23.1 “Configuration
Bits”.
Date Codes that pertain to this issue:
All engineering and production devices.
following
3FFFFEh:3FFFFFh
PIC18F87J10 Family Rev. A3 Silicon Errata
silicon
0001 0101 001
0001 0101 010
0001 0101 011
0001 0101 100
0001 0101 101
0001 0101 111
0001 0111 000
0001 0111 001
0001 0111 010
0001 0111 011
Device ID
errata apply
in
Revision ID
the
0 0100
0 0100
0 0100
0 0100
0 0100
0 0100
0 0100
0 0100
0 0100
0 0100
only
device’s
to
PIC18F87J10 FAMILY
2. Module: External Memory Bus
3. Module: External Memory Bus
For PIC18F8XJXX devices, the Stack Pointer may
incorrectly increment during a table read operation
if the external memory bus wait states are
enabled.
This is when:
• The Configuration bit, WAIT, is clear
• The WAITx bits (MEMCON<5:4>) are not equal
Work around
If using the external memory bus and performing
TBLRD operations with a non-zero wait state –
described by the preceding two bullet points – first
disable interrupts by clearing the GIE/GIEH
(INTCON<7>) and PEIE/GIEL (INTCON<6>) bits.
Date Codes that pertain to this issue:
All engineering and production devices.
The A<19:16> EMB address lines and read/write
control pins (OE, WRH and WRL) are released to
their respective inactive states at the same time
which violates the timing condition mentioned in
Figure 26-5 and Figure 26-6 in the data sheet.
This may result in the peripheral device on the bus
detecting an address change when write/read is
initiated. The bus capacitance and signal delay on
the address and control lines can affect the
probability of invalid detection.
Work around
Do one of the following:
• Use a latch based on the falling edge of ALE to
• Add a delay circuit to extend the valid time for
Date Codes that pertain to this issue:
All engineering and production devices.
(CONFIG3L<7> = 0)
to ‘11’
hold the A<19:16> signals.
A<19:16> signals to ensure the address is valid
until read/write signals go inactive.
DS80341A-page 1

Related parts for PIC18F87J10-I/PT

PIC18F87J10-I/PT Summary of contents

Page 1

... The PIC18F87J10 family parts you have received conform functionally to the Device Data Sheet (DS39663D), except for the anomalies described below. Any Data Sheet Clarification issues related to the PIC18F87J10 family will be reported in a separate Data Sheet errata. Please check the Microchip web site for any existing issues. The ...

Page 2

... PIC18F87J10 FAMILY 4. Module: Timer1 In 16-Bit Asynchronous Counter mode (with or without use of the Timer1 oscillator), the TMR1H and TMR3H buffers do not update when TMRxL is read. This issue only affects reading the TMRxH regis- ters. The timers increment and set the interrupt flags as expected and the Timer registers can be written as expected ...

Page 3

... To avoid producing the short pulse: 1. Turn off Timer2. 2. Clear the TMR2 register. 3. Load the SSPxBUF with the data to be transmitted. 4. Turn Timer2 back on. For sample code, see Example 1. © 2007 Microchip Technology Inc. PIC18F87J10 FAMILY EXAMPLE 1: LOOP BTFSS SSP1STAT, BF before CY BRA LOOP MOVF ...

Page 4

... PIC18F87J10 FAMILY 11. Module: Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) In rare situations, one or more extra zero bytes have been observed in a packet transmitted by the module operating in Asynchronous mode. The actual data is not lost or corrupted; only unwanted (extra) zero bytes are observed in the packet. ...

Page 5

... ADCON2 to WREG BSF ADCON2, ADCS0 ;temporarily select RC oscillator as clock BSF ADCON2, ADCS1 MOVWF ADCON2 ;restore ADCON2 to original value © 2007 Microchip Technology Inc. PIC18F87J10 FAMILY 15. Module: 10-Bit Analog-to-Digital (A/D) Converter When the A/D conversion clock is selected to be either F /64 OSC OSC OSC ...

Page 6

... PIC18F87J10 FAMILY 16. Module: 10-Bit Analog-to-Digital (A/D) Converter When selected as the A/D conversion OSC clock, A/D conversion will not be performed. Work around None. Date Codes that pertain to this issue: All engineering and production devices. DS80341A-page 6 REVISION HISTORY Rev A Document (8/2007) First release of this document. Includes silicon issues ...

Page 7

... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 8

... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2007 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...

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