DSPIC30F2010-20I/MM Microchip Technology, DSPIC30F2010-20I/MM Datasheet - Page 93
DSPIC30F2010-20I/MM
Manufacturer Part Number
DSPIC30F2010-20I/MM
Description
IC DSPIC MCU/DSP 12K 28QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2010-20ISO.pdf
(202 pages)
3.DSPIC30F2010-20ISO.pdf
(18 pages)
4.DSPIC30F2010-20ISO.pdf
(6 pages)
5.DSPIC30F2010-20ISO.pdf
(26 pages)
6.DSPIC30F2010-20IMM.pdf
(204 pages)
Specifications of DSPIC30F2010-20I/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
20
Flash Memory Size
12KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F2010-20I/MMG
DSPIC30F201020IMM
DSPIC30F201020IMM
DSPIC30F201020IMM
DSPIC30F201020IMM
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2010-20ISO PDF datasheet #2
- DSPIC30F2010-20ISO PDF datasheet #3
- DSPIC30F2010-20ISO PDF datasheet #4
- DSPIC30F2010-20ISO PDF datasheet #5
- DSPIC30F2010-20IMM PDF datasheet #6
- Current page: 93 of 202
- Download datasheet (3Mb)
15.3
The SSx pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode, with SSx
pin control enabled (SSEN = 1). When the SSx pin is
low, transmission and reception are enabled, and the
SDOx pin is driven. When SSx pin goes high, the SDOx
pin is no longer driven. Also, the SPI module is re-
synchronized, and all counters/control circuitry are
reset. Therefore, when the SSx pin is asserted low
again, transmission/reception will begin at the MSb,
even if SSx had been de-asserted in the middle of a
transmit/receive.
© 2011 Microchip Technology Inc.
Slave Select Synchronization
15.4
During Sleep mode, the SPI module is shut down. If
the CPU enters Sleep mode while an SPI transaction
is in progress, then the transmission and reception is
aborted.
The transmitter and receiver will stop in Sleep mode.
However, register contents are not affected by
entering or exiting Sleep mode.
15.5
When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPIxSTAT<13>)
selects if the SPI module will stop or continue on Idle.
If SPISIDL = 0, the module will continue to operate
when the CPU enters Idle mode. If SPISIDL = 1, the
module will stop when the CPU enters Idle mode.
SPI Operation During CPU Sleep
Mode
SPI Operation During CPU Idle
Mode
dsPIC30F2010
DS70118J-page 93
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