ATMEGA16A-MU Atmel, ATMEGA16A-MU Datasheet - Page 238
![MCU AVR 16K FLASH 16MHZ 44-QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA16A-MU
Manufacturer Part Number
ATMEGA16A-MU
Description
MCU AVR 16K FLASH 16MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA16A-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
44QFN EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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24.5.3
24.5.4
238
ATmega16A
Scanning the RESET Pin
Scanning the Clock Pins
Figure 24-5. Additional Scan Signal for the Two-wire Interface
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high
logic for High Voltage Parallel Programming. An observe-only cell as shown in
inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV.
Figure 24-6. Observe-only Cell
The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscilla-
tor, External RC, External Clock, (High Frequency) Crystal Oscillator, Low Frequency Crystal
Oscillator, and Ceramic Resonator.
Figure 24-7
The Enable signal is supported with a general boundary-scan cell, while the Oscillator/Clock out-
put is attached to an observe-only cell. In addition to the main clock, the Timer Oscillator is
scanned in the same way. The output from the internal RC Oscillator is not scanned, as this
Oscillator does not have external connections.
From System Pin
shows how each Oscillator with external connection is supported in the scan chain.
Pxn
Previous
From
Cell
ShiftDR
0
1
ClockDR
D
Slew-rate Limited
FF1
Q
Next
SRC
Cell
To
To System Logic
OCxn
ODxn
TWIEN
IDxn
PUExn
Figure 24-6
8154B–AVR–07/09
is
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