DSPIC30F3012-20I/SO Microchip Technology, DSPIC30F3012-20I/SO Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F3012-20I/SO
• Description: IC DSPIC MCU/DSP 24K 18SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3012-20I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 12
• Flash Memory Size: 24KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC30F005 - MODULE SCKT DSPIC30F 18DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F301220ISO

dsPIC30F3012/3013
10. 4x and 8x PLL Mode
11. Sleep Mode
12. I
13. I/O Port – Port Pin Multiplexed with IC1
14. I
15. Timer Module
DS80255F-page 2
If 4x or 8x PLL mode is used, the input frequency
range is 5 MHz-10 MHz instead of 4 MHz-10 MHz.
Execution of the Sleep instruction (PWRSAV #0)
may cause incorrect program operation after the
device wakes up from Sleep. The current
consumption during Sleep may also increase
beyond the specifications listed in the device data
sheet.
The I
operating as an I
The Port I/O pin multiplexed with the Input Capture
1 (IC1) function cannot be used as a digital input
pin when the UART auto-baud feature is enabled.
When the I
addressing using the same address bits (A10 and
A9) as other I
not work as expected.
Clock switching prevents the device from waking
up from Sleep.
2
2
C™ Module
C Module: 10-bit addressing mode
2
C module loses incoming data bytes when
2
C module is configured for 10-bit
2
C devices, the A10 and A9 bits may
2
C slave.
16. PLL Lock Status Bit
17. PSV Operations
18. I
19. I
20. I
The following sections describe the errata and work
around to these errata, where they may apply.
The PLL LOCK Status bit (OSCCON<5>) can
occasionally get cleared and generate an
oscillator failure trap even when the PLL is still
locked and functioning correctly.
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register, on address match if the
least significant bits of the address are the same
as the 7-bit reserved addresses.
When the I
slave with an address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather than 0x02.
When the I
device generates a glitch on the SDA and SCL
pins, causing a false communication start in a
single-master configuration or a bus collision in a
multi-master configuration.
2
2
2
C Module: 10-bit Addressing Mode
C Module: 10-bit Addressing Mode
C Module
2
2
C module is enabled, the dsPIC
C module is configured as a 10-bit
© 2008 Microchip Technology Inc.
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