DSPIC30F2010-30I/SP Microchip Technology, DSPIC30F2010-30I/SP Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F2010-30I/SP
• Description: IC DSPIC MCU/DSP 12K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-30I/SP

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F2010-30I; DSPIC30F2010-30I; DSPIC30F2010-30I/SPG; DSPIC30F201030ISP

dsPIC30F2010
TABLE 2:
DS80451E-page 2
Note 1:
Operations
Watchdog
Controller
Compare
Compare
Interrupt
Module
Output
Output
Timer
Timer
CPU
CPU
CPU
CPU
CPU
CPU
ADC
ADC
PSV
PLL
PLL
Only those issues indicated in the last column apply to the current silicon revision.
Y Data Space
Modification
32-bit Mode
Sleep Mode
PWM Mode
Instructions
Conversion
Instruction
Nested DO
Instruction
MAC Class
Triggered
4x Mode
8x Mode
Address
Feature
REPEAT
SILICON ISSUE SUMMARY
with +4
DAW.b
Loops
DISI
Loop
—
—
—
—
Number
Item
10.
12.
13.
14.
15.
16.
11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
When an instruction that writes to a location in the
address range of Y data memory is immediately
followed by a MAC-type DSP instruction that reads a
location also resident in Y data memory, the operations
will not be performed as specified.
Sequential MAC instructions, which prefetch data from Y
data space using +4 address modification will cause an
address error trap.
The Decimal Adjust instruction, DAW.b, may improperly
clear the Carry bit, C (SR<0>).
In certain instructions, fetching one of the operands from
program memory using Program Space Visibility (PSV)
will corrupt specific bits in the STATUS Register, SR.
When using two DO loops in a nested fashion,
terminating the inner-level DO loop by setting the EDT bit
(CORCON<11>) will produce unexpected results.
When a REPEAT loop is interrupted by two or more
interrupts in a nested fashion, an address error trap may
be caused.
The DISI instruction will not disable interrupts if a DISI
instruction is executed in the same instruction cycle that
the DISI counter decrements to zero.
The 32-bit general purpose timers do not function as
specified for prescaler ratios other than 1:1.
The Output Compare module will produce a glitch when
loading a 0% duty cycle in PWM mode. It will also miss
the next compare after the glitch.
The Output Compare module will produce a glitch on
the output when an I/O pin is initially set high and the
module is configured to drive the pin low at a specified
time.
Sampling multiple channels sequentially using any
conversion trigger other than the auto-convert feature
requires the SAMC bits to be non-zero.
ADC event triggers from the INT0 pin will not wake-up the
device from Sleep mode if the SMPIx bits are non-zero.
The Watchdog Timer does not function as specified.
The 4x PLL mode of operation may not function
correctly for certain input frequencies.
An interrupt occurring immediately after modifying the
CPU IPL, interrupt IPL, interrupt enable or interrupt flag
may cause an address error trap.
If 8x PLL mode is used, the input frequency range is
5 MHz-10 MHz instead of 4 MHz-10 MHz.
Issue Summary
© 2010 Microchip Technology Inc.
A0 A1 A2 A3 A4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Revisions
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X