PIC16C745-I/SP Microchip Technology, PIC16C745-I/SP Datasheet
PIC16C745-I/SP
Specifications of PIC16C745-I/SP
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PIC16C745-I/SP Summary of contents
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... RC2/CCP1 Peripheral Features: • Universal Serial Bus (USB 1.1) - Soft attach/detach • 64 bytes of USB dual port RAM • 22 (PIC16C745 (PIC16C765) I/O pins - Individual direction control - 1 high voltage open drain (RA4 PORTB pins with: - Interrupt-on-change control (RB<7:4> only) - Weak pull-up control - 3 pins dedicated to USB • ...
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... RC7/RX/DT 10 RB2 RB3 11 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/ RD3/PSP3 RD2/PSP2 PIC16C745 6 MHz or 24 MHz POR, BOR (PWRT, OST) 8K 256 (Ports channel x 8 bit — USB, USART/SCI Yes Preliminary RC0/T1OSO/T1CKI 31 OSC2/CLKOUT 30 OSC1/CLKIN ...
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... Table of Contents 1.0 General Description .............................................................................................................................................. 5 2.0 PIC16C745/765 Device Varieties ......................................................................................................................... 7 3.0 Architectural Overview .......................................................................................................................................... 9 4.0 Memory Organization.......................................................................................................................................... 15 5.0 I/O Ports.............................................................................................................................................................. 31 6.0 Timer0 Module .................................................................................................................................................... 43 7.0 Timer1 Module .................................................................................................................................................... 45 8.0 Timer2 Module .................................................................................................................................................... 49 9.0 Capture/Compare/PWM Modules ....................................................................................................................... 51 10.0 Universal Serial Bus............................................................................................................................................ 57 11.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) ............................................................. 77 12 ...
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... PIC16C745/765 NOTES: DS41124C-page 4 Preliminary 2000 Microchip Technology Inc. ...
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... Synchronous Asynchronous Receiver Transmitter (USART) is also known as the Serial Communications Interface or SCI. Also, a 5-channel high-speed 8-bit A/D is provided on the PIC16C745, while the PIC16C765 offers 8 channels. The 8-bit resolution is ideally suited for applications requiring a low cost ana- log interface (e.g., thermostat control, pressure sens- ing, etc ...
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... PIC16C745/765 NOTES: DS41124C-page 6 Preliminary 2000 Microchip Technology Inc. ...
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... A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C745/765 Product Identification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number. ...
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... PIC16C745/765 NOTES: DS41124C-page 8 Preliminary 2000 Microchip Technology Inc. ...
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... The PIC16C745/765 can directly or indirectly address its register files or data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16C745/765 has an orthog- onal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘ ...
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... OSC1/ CLKIN Timing Generation OSC2/ x4 PLL CLKOUT MCLR Timer0 Timer1 CCP2 CCP1 Note 1: Higher order bits are from the STATUS register. 2: Not available on PIC16C745. DS41124C-page 10 8 Data Bus Program Counter RAM 8 Level Stack File (13 bit) Registers 256 x 8 RAM Addr(1) 9 Addr MUX ...
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... TABLE 3-1: PIC16C745/765 PINOUT DESCRIPTION Name Function MCLR MCLR OSC1 OSC1/CLKIN CLKIN OSC2 OSC2/CLKOUT CLKOUT RA0 RA0/AN0 AN0 RA1 RA1/AN1 AN1 RA2 RA2/AN2 AN2 RA3 RA3/AN3/V AN3 REF V REF RA4 RA4/T0CKI T0CKI RA5 RA5/AN4 AN4 RB0 RB0/INT INT RB1 RB1 RB2 ...
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... PIC16C745/765 TABLE 3-1: PIC16C745/765 PINOUT DESCRIPTION (CONTINUED) Name Function RC6 RC6/TX/ RC7 RC7/RX/ RD0 RD0/PSP0 PSP0 RD1 RD1/PSP1 PSP1 RD2 RD2/PSP2 PSP2 RD3 RD3/PSP3 PSP3 RD4 RD4/PSP4 PSP4 RD5 RD5/PSP5 PSP5 RD6 RD6/PSP6 PSP6 RD7 RD7/PSP7 PSP7 RE0 RE0/RD/AN5 RD AN5 RE1 ...
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... All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. 2000 Microchip Technology Inc. PIC16C745/765 3.2 Instruction Flow/Pipelining An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4) ...
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... PIC16C745/765 NOTES: DS41124C-page 14 Preliminary 2000 Microchip Technology Inc. ...
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... MEMORY ORGANIZATION 4.1 Program Memory Organization The PIC16C745/765 has a 13-bit program counter capable of addressing program memory space. All devices covered by this data sheet have bits of program memory. The address range is 0000h - 1FFFh for all devices. The reset vector is at 0000h and the interrupt vector is at 0004h ...
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... Unimplemented data memory locations, read as ‘0’. *Not a physical register. Note 1: Reserved registers may contain USB state information. 2: Parallel slave ports (PORTD and PORTE) not implemented on PIC16C745; always maintain these bits clear. DS41124C-page 16 File Bank 2 File Bank 3 Address Address 80h Indirect addr ...
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... Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 3: These registers can be addressed from any bank. 4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear. 2000 Microchip Technology Inc. The Special Function Registers can be classified into two sets (core and peripheral). Those registers associ- ated with the “ ...
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... Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 3: These registers can be addressed from any bank. 4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear. DS41124C-page 18 Bit 5 ...
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... Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 3: These registers can be addressed from any bank. 4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear. 2000 Microchip Technology Inc. PIC16C745/765 ...
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... Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 3: These registers can be addressed from any bank. 4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear. DS41124C-page 20 Bit 5 ...
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... Legend unknown unchanged value depends on condition unimplemented read as ’0’. Shaded locations are unimplemented, read as ‘0’. Note 1: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 2000 Microchip Technology Inc. PIC16C745/765 Bit 5 Bit 4 Bit 3 Bit 2 PID3 ...
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... PIC16C745/765 4.2.2.1 STATUS REGISTER The STATUS register, shown in Register 4-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS ...
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... Microchip Technology Inc. Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. R/W-1 R/W-1 R/W-1 R/W-1 PSA PS2 PS1 PS0 128 Preliminary PIC16C745/765 R = Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR reset DS41124C-page 23 ...
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... PIC16C745/765 4.2.2.3 INTCON REGISTER The INTCON register is a readable and writable regis- ter, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and external RB0/INT pin interrupts. REGISTER 4-3: INTERRUPT CONTROL REGISTER (INTCON: 10Bh, 18Bh) R/W-0 ...
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... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: Parallel slave ports not implemented on the PIC16C745; always maintain this bit clear. 2000 Microchip Technology Inc. PIC16C745/765 Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt ...
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... TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software TMR1 register did not overflow Note 1: Parallel slave ports not implemented on the PIC16C745; always maintain this bit clear. DS41124C-page 26 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
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... A TMR1 register capture occurred (must be cleared in software TMR1 register capture occurred Compare Mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM Mode Unused 2000 Microchip Technology Inc. PIC16C745/765 U-0 U-0 U-0 R/W-0 — — — ...
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... PIC16C745/765 4.2.2.8 PCON REGISTER The Power Control (PCON) register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT) and an external MCLR Reset. REGISTER 4-8: POWER CONTROL REGISTER REGISTER (PCON: 8Eh) U-0 U-0 U-0 U-0 — ...
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... Refer to the application note “Implementing a Table Read" (AN556). 4.3.2 STACK The PIC16C745/765 family has an 8-level deep x 13- bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an inter- rupt causes a branch ...
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... PIC16C745/765 4.5 Indirect Addressing, INDF and FSR Registers The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF reg- ister. Any instruction using the INDF register actually accesses the register pointed to by the File Select Reg- ister, FSR. Reading the INDF register itself indirectly (FSR = ’ ...
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... Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. On the PIC16C745/765, PORTA pins are multiplexed with analog inputs and analog V input. The opera- REF tion of each pin is selected by clearing/setting the con- trol bits in the ADCON1 register (A/D Control Register1) ...
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... PIC16C745/765 TABLE 5-1: PORTA FUNCTIONS Name Function RA0 RA0/AN0 AN0 RA1 RA1/AN1 AN1 RA2 RA2/AN2 AN2 RA3 RA3/AN3/V AN3 REF V REF RA4 RA4/T0CKI T0CKI RA5 RA5/AN4 AN4 Legend open drain Schmitt Trigger TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Address Name ...
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... Any read or write of PORTB. This will end the mismatch condition. b) Clear flag bit RBIF. 2000 Microchip Technology Inc. PIC16C745/765 A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. This interrupt-on-mismatch feature, together with soft- ...
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... PIC16C745/765 TABLE 5-3: PORTB FUNCTIONS Name Function RB0 RB0/INT INT RB1 RB1 RB2 RB2 RB3 RB3 RB4 RB4 RB5 RB5 RB6 RB6/ICSPC ICSPC RB7 RB7/ICSPD ICSPD Legend open drain Schmitt Trigger TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Address Name Bit 7 ...
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... BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. 2000 Microchip Technology Inc. PIC16C745/765 FIGURE 5-5: PORTC BLOCK DIAGRAM (1) Port/Peripheral Select Peripheral Data Out ...
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... PIC16C745/765 TABLE 5-5: PORTC FUNCTIONS Name Function RC0 RC0/T1OSO/T1CKI T1OSO T1CKI RC1 RC1/T1OSI/CCP2 T1OSI CCP2 RC2 RC2/CCP1 CCP1 RC6 RC6/TX/ RC7 RC7/RX/ Legend open drain Schmitt Trigger TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Address Name Bit 7 Bit 6 07h PORTC RC7 ...
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... PORTD and TRISD Registers Note: The PIC16C745 does not provide PORTD. The PORTD and TRISD registers are reserved. Always maintain these bits clear. PORTD is an 8-bit port with Schmitt Trigger input buff- ers. Each pin is individually configured as an input or output. ...
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... PIC16C745/765 5.5 PORTE and TRISE Registers Note 1: The PIC16C745 does PORTE. The PORTE and TRISE registers are reserved. Always maintain these bits clear. PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configured as inputs or outputs. These pins have Schmitt Trigger input buffers ...
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... IBF OBF IBOV TRISE 9Fh ADCON1 — — Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by PORTE. Note 1: PIC16C765 only. 2000 Microchip Technology Inc. PIC16C745/765 (1) U-0 R/W-1 R/W-1 R/W-1 — TRISE2 TRISE1 TRISE0 Bit 4 Bit 3 Bit 2 Bit 1 — ...
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... PIC16C745/765 5.6 Parallel Slave Port (PSP) Note: The PIC16C745 does not provide a paral- lel slave port. The PORTD, PORTE, TRISD and TRISE registers are reserved. Always maintain these bits clear. PORTD operates as an 8-bit wide Parallel Slave Port (PSP), or microprocessor port when control bit PSP- MODE (TRISE< ...
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... INTCON GIE PEIE Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745. Always maintain these bits clear. 2: PIC16C765 only. 2000 Microchip Technology Inc ...
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... PIC16C745/765 NOTES: DS41124C-page 42 Preliminary 2000 Microchip Technology Inc. ...
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... Timer PSA WDT Enable bit Note: T0CS, T0SE, PSA, PS<2:0> are (OPTION_REG<5:0>). 2000 Microchip Technology Inc. PIC16C745/765 Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 (OPTION_REG< ...
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... PIC16C745/765 6.2 Using Timer0 with an External Clock When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore ...
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... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: On the rising edge after the first falling edge. 2000 Microchip Technology Inc. PIC16C745/765 In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON< ...
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... PIC16C745/765 7.1 Timer1 Operation in Timer Mode Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer The synchronize control bit T1SYNC INT (T1CON<2>) has no effect since the internal clock is always in sync. FIGURE 7-1: TIMER1 BLOCK DIAGRAM ...
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... It will continue to run during SLEEP primarily intended for use with a 32 kHz crystal. Table 7-1 shows the capacitor selection for the Timer1 oscillator. 2000 Microchip Technology Inc. PIC16C745/765 TABLE 7-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Osc Type ...
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... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the Timer1 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear. DS41124C-page 48 Bit 5 Bit 4 Bit 3 ...
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... T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 2000 Microchip Technology Inc. PIC16C745/765 8.1 Timer2 Prescaler and Postscaler The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • a write to the T2CON register • ...
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... PR2 Timer2 Period Register Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the Timer2 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear. DS41124C-page 50 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 T0IE ...
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... Capture None. PWM Compare None. 2000 Microchip Technology Inc. PIC16C745/765 CCP2 Module: Capture/Compare/PWM Register1 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is generated by a compare match and will reset Timer1 and start an A/D conversion (if the A/D module is enabled) ...
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... PIC16C745/765 REGISTER 9-1: CAPTURE/COMPARE/PWM CONTROL REGISTER (CCP1CON: 17H, CCP2CON: 1Dh R/W-0 R/W-0 — — DCnB1 DCnB0 CCPnM3 bit7 bit 7-6: Unimplemented: Read as '0' bit 5-4: DCnB<1:0>: PWM Least Significant bits Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRnL. ...
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... Enable edge detect TMR1H CCP1CON<3:0> Q’s 2000 Microchip Technology Inc. PIC16C745/765 9.1.2 TIMER1 MODE SELECTION Timer1 must be running in timer mode or synchronized counter mode for the CCP module to use the capture feature. In asynchronous counter mode, the capture operation may not work. ...
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... PIC16C745/765 9.2 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: • Driven high • Driven low • Remains unchanged The action on the pin is based on the value of control bits CCP1M< ...
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... PWM duty cycle. This double buffering is essential for glitchless PWM operation. 2000 Microchip Technology Inc. PIC16C745/765 When the CCPR1H and 2-bit latch match TMR2 con- catenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. ...
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... Capture/Compare/PWM register2 (MSB) 1Dh CCP2CON — — Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear. DS41124C-page 56 Bit 5 Bit 4 Bit 3 Bit 2 T0IE ...
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... Control Transfers are used for configuration purposes. 2000 Microchip Technology Inc. PIC16C745/765 10.1.2 FRAMES Information communicated on the bus is grouped in a format called Frames. Each Frame duration and is composed of multiple transfers. Each transfer type can be repeated more than once within a frame ...
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... USB website at www.usb.org. DS41124C-page 58 10.2 Introduction The PIC16C745/765 USB peripheral module supports Low Speed control and interrupt (IN and OUT) trans- fers only. The implementation supports 3 endpoint numbers ( for a total of 6 endpoints. The following terms are used in the description of the USB module: • ...
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... FIGURE 10-1: USB TOKENS USB RESET USB_RST Interrupt Generated SETUP TOKEN IN TOKEN OUT TOKEN = Host = Device 2000 Microchip Technology Inc. PIC16C745/765 DATA ACK DATA ACK DATA ACK Preliminary TOK_DNE Interrupt Generated TOK_DNE Interrupt Generated TOK_DNE Interrupt Generated DS41124C-page 59 ...
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... PIC16C745/765 10.5 USB Register Map The USB Control Registers, Buffer Descriptors and Buffers are located in Bank 3. 10.5.1 CONTROL AND STATUS REGISTERS The USB module is controlled by 7 registers, plus those that control each endpoint and endpoint/ direction buffer. REGISTER 10-1: USB INTERRUPT FLAGS REGISTER (UIR: 190h) ...
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... ERROR interrupt enabled 0 = ERROR interrupt disabled bit 0: USB_RST: Set to enable USB_RST interrupts 1 = USB_RST interrupt enabled 0 = USB_RST interrupt disabled Note 1: This interrupt is the only interrupt active during UCTRL.SUSPEND = 1. 2000 Microchip Technology Inc. PIC16C745/765 R/W-0 R/W-0 R/W-0 R/W-0 TOK_DNE ACTIVITY UERR USB_RST Preliminary ...
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... PIC16C745/765 10.5.1.3 USB Error Interrupt Status Register (UEIR) The USB Error Interrupt Status Register (UEIR) con- tains bits for each of the error sources within the USB. Each of these bits are enabled by their respective error enable bits (UEIE). The result is OR’ed together and sent to the ERROR bit of the UIR register ...
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... CRC5: Set this bit to enable CRC5 interrupts 1 = CRC5 interrupt enabled 0 = CRC5 interrupt disabled bit 0: PID_ERR: Set this bit to enable PID_ERR interrupts 1 = PID_ERR interrupt enabled 0 = PID_ERR interrupt disabled 2000 Microchip Technology Inc. PIC16C745/765 R/W-0 R/W-0 R/W-0 R/W-0 DFN8 CRC16 CRC5 PID_ERR ...
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... PIC16C745/765 10.5.1.5 Status Register (USTAT) The USB Status Register reports the transaction sta- tus within the USB. When the MCU recognizes a TOK_DNE interrupt, this register should be read to determine the status of the previous endpoint commu- nication. The data in the status register is valid when the TOK_DNE interrupt bit is asserted ...
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... The V USB driven, however the transceiver outputs are disabled USB module in power conserve mode 0 = USB module normal operation bit 0: Unimplemented: Read as ’0’ 2000 Microchip Technology Inc. PIC16C745/765 R/W-0 R/W-0 R/W-0 U-0 — bit0 pin will be driven with 3.3V (nominal) ...
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... PIC16C745/765 10.5.1.7 USB Address Register (UADDR) The Address Register (UADDR) contains the unique USB address that the USB will decode. The register is reset to 00h after the RESET input has gone active or the USB has decoded a USB Reset signaling. That will initialize the address register to decode address 00h as required by the USB specification ...
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... USB to return a STALL handshake. The EP_STALL bit can be set or cleared by the SIE. Refer to the USB 1.1 Specification, Sections 4.4.4 and 8.5.2 for more details on the STALL protocol. 2000 Microchip Technology Inc. PIC16C745/765 10.5.1.10 USB Endpoint Control Register (EPCn) The Endpoint Control Register contains the endpoint Buffer control bits for each of the 6 endpoints available on USB for a decoded address ...
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... PIC16C745/765 10.6 Buffer Descriptor Table (BDT) To efficiently manage USB endpoint communications the USB implements a Buffer Descriptor Table (BDT) in register space. Every endpoint requires a 4 byte Buffer Descriptor (BD) entry. Because the buffers are shared between the MCU and the USB, a simple semaphore mechanism is used to distinguish which is allowed to update the BD and buffers in system mem- ory ...
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... BD in this location. The BD is not consumed by the SIE (the own bit remains and the rest of the BD are unchanged) when a BSTALL bit is set. bit 1-0: Reserved: Read as ’X’ Note: Recommend that users not use BSF, BCF due to the dual functionality of this register. 2000 Microchip Technology Inc. PIC16C745/765 W-X W-X U-X U-X DTS BSTALL — ...
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... PIC16C745/765 REGISTER 10-11: BUFFER DESCRIPTOR STATUS. BITS READ BY THE MCU (BDndST: 1A0h, 1A4h, 1A8h, 1ACh, 1B0h, 1B4h) R/W-0 R/W-X R/W-X R/W-X UOWN DATA0/1 PID3 PID2 bit7 bit 7: UOWN: USB Own This UOWN bit determines who currently owns the buffer. The SIE writes this bit when it has com- pleted a token ...
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... BA1 BA0 bit0 FIGURE 10-2: EXTERNAL CIRCUITRY APPLICATION PIC16C745/765 V USB D- D+ Note: The PIC16C745/765 requires an external resistor and capacitor to communicate with a host over USB. 10.7.1.1 V Output USB The V provides a 3.3V nominal output. This drive USB current is sufficient for a pull-up only. 10.8 ...
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... RAM in banks zero and one, plus half of bank two, available for your application to use. 10.9.3.5 Common RAM Usage The PIC16C745/765 has 16 bytes of common RAM. These are the last 16 addresses in each bank and all refer to the same 16 bytes of memory, without regard to which register bank is currently addressed by the RP0, RP1 and IRP bits ...
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... Buffer Allocation The PIC16C745/765 has 64 bytes of Dual Port RAM. 24 are used for the Buffer Descriptor Table (BDT), leaving 40 bytes for buffers. Endpoints 0 IN and OUT need dedicated buffers since a setup transaction can never be NAKed. That leaves three buffers for four possible Endpoints, but the USB spec requires that low speed devices are only allowed 2 endpoints (USB 1 ...
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... PIC16C745/765 ConfiguredUSB (Macro) continuously polls the enu- meration status bits and waits until the device has been configured by the host. This should be used after the call to InitUSB and prior to the first time your application attempts to communicate on the bus. SetConfiguration is a callback function that allows your application to associate some meaning to a Set Configuration command from the host ...
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... USB_MAIN.ASM - Sample interrupt service routine. • HIDCLASS.ASM - Handles the HID class specific commands. 2000 Microchip Technology Inc. PIC16C745/765 enumeration is complete, and then polls EP1 OUT to see if there is any data available. When a buffer is available copied to the IN buffer. Presumably your application would do something more interesting with the data than this example ...
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... PIC16C745/765 NOTES: DS41124C-page 76 Preliminary 2000 Microchip Technology Inc. ...
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... TSR full bit 0: TX9D: 9th bit of transmit data. (Can be used for parity.) 2000 Microchip Technology Inc. PIC16C745/765 as a half duplex synchronous system that can commu- nicate with peripheral devices, such as A/D or D/A inte- grated circuits, Serial EEPROMs, etc. The USART can be configured in the following modes: • ...
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... PIC16C745/765 REGISTER 11-2: RECEIVE STATUS AND CONTROL REGISTER (RCSTA: 18h) R/W-0 R/W-0 R/W-0 R/W-0 SPEN RX9 SREN CREN bit7 bit 7: SPEN: Serial Port Enable bit 1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins Serial port disabled bit 6: RX9: 9-bit Receive Enable bit ...
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... Microchip Technology Inc. PIC16C745/765 It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks. This is because the F /(16(X + 1)) equation can reduce the INT baud rate error in some cases. Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared) ...
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... PIC16C745/765 TABLE 11-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) 24 MHz Desired Actual Baud % of Error Baud 300 1200 2400 4800 9600 9615.38 0.16 19200 19230.77 0.16 38400 38461.54 0.16 57600 57692.31 0.16 115200 115384.62 0.16 230400 250000.00 8.51 460800 500000.00 8.51 ...
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... Baud Rate CLK SPBRG Baud Rate Generator 2000 Microchip Technology Inc. PIC16C745/765 ( PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in soft- ware. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicated the sta- tus of the TXREG register, another bit TRMT (TXSTA< ...
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... SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear. DS41124C-page 9-bit transmission is desired, then set transmit bit TX9 ...
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... Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. 2000 Microchip Technology Inc. PIC16C745/765 possible for two bytes of data to be received and trans- ferred to the RCREG FIFO and a third byte to begin shifting to the RSR register ...
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... SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear. DS41124C-page 84 6. Flag bit RCIF will be set when reception is com- plete and an interrupt will be generated if enable bit RCIE was set ...
Page 85
... TXREG register will result in an immediate transfer to TSR resulting in an empty TXREG. Back-to-back transfers are possible. 2000 Microchip Technology Inc. PIC16C745/765 Clearing enable bit TXEN, during a transmission, will cause the transmission to be aborted and will reset the transmitter. The DT and CK pins will revert to hi- impedance ...
Page 86
... Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear. FIGURE 11-6: SYNCHRONOUS TRANSMISSION Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4 ...
Page 87
... Baud Rate Generator Register Legend unknown unimplemented read as '0'. Shaded cells are not used for synchronous master reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear. 2000 Microchip Technology Inc essential to clear bit OERR set. The ninth receive bit is buffered the same way as the receive data ...
Page 88
... PIC16C745/765 FIGURE 11-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN RC7/RX/DT pin bit0 RC6/TX/CK pin Write to bit SREN SREN bit ’0’ CREN bit RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = ’1’ and bit BRG = ’0’. ...
Page 89
... If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register. 2000 Microchip Technology Inc. PIC16C745/765 11.4.2 USART SYNCHRONOUS SLAVE RECEPTION The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode. Also, bit SREN is a don’ ...
Page 90
... CSRC TX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented read as '0'. Shaded cells are not used for synchronous slave reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear. DS41124C-page 90 Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 91
... ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The 8-bit Analog-To-Digital (A/D) converter module has five inputs for the PIC16C745 and eight for the PIC16C765. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital value. The output of the sample and hold is the input into the converter, which generates the result via successive approximation ...
Page 92
... PIC16C745/765 REGISTER 12-1: A/D CONTROL REGISTER (ADCON0: 1Fh) R/W-0 R/W-0 R/W-0 R/W-0 ADCS1 ADCS0 CHS2 CHS1 bit7 bit 7-6: ADCS<1:0>: A/D Conversion Clock Select bits INT INT ( /32 INT (clock derived from dedicated internal oscillator) RC bit 5-3: CHS<2:0>: Analog Channel Select bits ...
Page 93
... A A 000 001 010 011 100 101 11x A = Analog input D = Digital I/O Note 1: A/D channels 5, 6 and 7 are implemented on the PIC16C765 only. 2000 Microchip Technology Inc. PIC16C745/765 U-0 R/W-0 R/W-0 R/W-0 — PCFG2 PCFG1 PCFG0 AN4 AN3 AN2 AN1 AN0 REF ...
Page 94
... Wait the required acquisition time. FIGURE 12-1: A/D BLOCK DIAGRAM A/D Converter V REF (Reference voltage) Note 1: Not available on PIC16C745. DS41124C-page 94 4. Start conversion: • Set GO/DONE bit (ADCON0) 5. Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR • ...
Page 95
... Manual (DS33023). In general, however, given a max of 10k and a worst case temperature of 100°C, T will be no more than 16µsec Sampling Switch leakage V = 0.6V T ± 500 In(1/511) S Preliminary PIC16C745/765 the minimum acquisition time, , see ACQ ACQ SS C HOLD = DAC capacitance = 51 Sampling Switch (k ) DS41124C-page 95 ...
Page 96
... Analog levels on any pin that is defined as a digital input, but not as an analog input, may cause the input buffer to consume current that is out of specification. 3: The TRISE register is not provided on the PIC16C745. DS41124C-page 96 12.4 A/D Conversions . The AD Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D ...
Page 97
... Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used for A/D conversion. Note 1: These bits are reserved on the PIC6C745; always maintain these bits clear. 2000 Microchip Technology Inc. PIC16C745/765 overhead (moving the ADRES to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the “ ...
Page 98
... PIC16C745/765 NOTES: DS41124C-page 98 Preliminary 2000 Microchip Technology Inc. ...
Page 99
... Code protection • ID locations • In-Circuit Serial Programming™ (ICSP) The PIC16C745/765 has a Watchdog Timer, which can be shut off only through configuration bits. It runs off its own dedicated RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. ...
Page 100
... PIC16C745/765 13.2 Oscillator Configurations 13.2.1 OSCILLATOR TYPES The PIC16C745/765 can be operated in four different oscillator modes. The user can program a configuration bit (FOSC0) to select one of these four modes: • EC External Clock • E4 External Clock with internal PLL enabled • HS High Speed Crystal/Resonator • ...
Page 101
... EXTERNAL CLOCK mode, users may directly drive the PIC16C745/ 765 provided that this external clock source meets the AC/DC timing requirements listed in Section 17.4. Figure 13-2 below shows how an external clock circuit should be configured. FIGURE 13-2: EXTERNAL CLOCK INPUT OPERATION (EC OSC ...
Page 102
... PIC16C745/765 FIGURE 13-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR SLEEP WDT Time-out Module Reset Power-on Reset V rise DD detect V DD Brown-out Reset OST/PWRT OST 10-bit Ripple counter OSC1 PWRT Dedicated 10-bit Ripple counter On-chip RC OSC DS41124C-page 102 Enable PWRT ...
Page 103
... This ensures that the crystal oscillator or resona- tor has started and stabilized. The OST time-out is invoked only for HS mode and only on Power-on Reset or wake-up from SLEEP. 2000 Microchip Technology Inc. PIC16C745/765 13.4.4 BROWN-OUT RESET (BOR falls below V (parameter D005) for longer ...
Page 104
... PIC16C745/765 13.5 Time-out in Various Situations TABLE 13-3: RESET TIME-OUTS POR Oscillator Configuration PWRTE = 1024 T PWRT OSC PWRT PLLRT 1024 T OSC EC T PWRT PWRT PLLRT TABLE 13-4: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD Power-on Reset Illegal set on POR Illegal set on POR ...
Page 105
... When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 13-5 for RESET value for specific condition. 4: PIC16C765 only. 2000 Microchip Technology Inc. PIC16C745/765 MCLR Resets WDT Reset uuuu uuuu N/A ...
Page 106
... PIC16C745/765 TABLE 13-7: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset Register Brown-out Reset (4) 1111 1111 TRISD (4) 0000 -111 TRISE PIE1 0000 0000 PIE2 ---- ---0 PCON ---- --0q PR2 1111 1111 TXSTA 0000 -010 SPBRG 0000 0000 ADCON1 ---- -000 UIR --00 0000 UIE --00 0000 UEIR ...
Page 107
... Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. 2000 Microchip Technology Inc. PIC16C745/765 Note interrupt occurs while the Global Interrupt Enable (GIE) bit is being cleared, the GIE bit may unintentionally be re- enabled by the user’ ...
Page 108
... USBIF USBIE CCP1IF CCP1IE TMR2IF TMR2IE TMR1IF TMR1IE CCP2IF CCP2IE The following table shows the interrupts for each device. Device T0IF INTF RBIF PSPIF PIC16C745 Yes Yes Yes PIC16C765 Yes Yes Yes Note 1: PIC16C765 only. DS41124C-page 108 (2) T OST Interrupt Latency ...
Page 109
... SWAPF W_TEMP,W ; swapf loads W without affecting STATUS flags RETFIE 2000 Microchip Technology Inc. PIC16C745/765 13.7 Context Saving During Interrupts During an interrupt, only the PC is saved on the stack. At the very least, W and STATUS should be saved to preserve the context for the interrupted program. All registers that may be corrupted by the ISR, such as PCLATH or FSR, should be saved ...
Page 110
... PIC16C745/765 13.8 Watchdog Timer (WDT) The Watchdog Timer is a free running on-chip dedi- cated oscillator, which does not require any external components. The WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction ...
Page 111
... A/D conversion (when A/D clock source is dedi- cated internal oscillator). 6. USART (Synchronous Slave mode). 2000 Microchip Technology Inc. PIC16C745/765 Other peripherals cannot generate interrupts, since during SLEEP, no on-chip Q clocks are present. When the SLEEP instruction is being executed, the next instruction ( pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...
Page 112
... PIC16C745/765 FIGURE 13-8: WAKE-UP FROM SLEEP THROUGH INTERRUPT OSC1 (4) CLKOUT INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC+1 Instruction Inst( Inst(PC) = SLEEP fetched Instruction Inst( SLEEP executed Note 1: HS oscillator mode assumed 1024T (drawing not to scale). This delay is not present in EC osc mode. ...
Page 113
... Register bit field In the set of i talics User defined term (font is courier) 2000 Microchip Technology Inc. PIC16C745/765 The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations All instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction ...
Page 114
... PIC16C745/765 TABLE 14-2: PIC16CXX INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW - Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ f, d Increment f, Skip if 0 ...
Page 115
... Operation: (W) .AND. (k) (W) Status Affected: Z Description: The contents of W register are AND’ed with the eight bit literal 'k'. The result is placed in the W register. 2000 Microchip Technology Inc. PIC16C745/765 ANDWF AND W with f Syntax: [label] ANDWF Operands 127 d Operation: (W) .AND. (f) Status Affected: ...
Page 116
... PIC16C745/765 BTFSS Bit Test f, Skip if Set Syntax: [label] BTFSS f,b Operands 127 0 b < 7 Operation: skip if (f<b> Status Affected: None Description: If bit ’b’ in register ’f’ is ’0’, the next instruction is executed. If bit ’b’ is ’1’, then the next instruc- ...
Page 117
... W register. If ’d’ the result is placed back in reg- ister ’f’. If the result is 1, the next instruc- tion is executed. If the result is 0, then a NOP is executed instead making instruction. CY 2000 Microchip Technology Inc. PIC16C745/765 GOTO Unconditional Branch Syntax: [ label ] Operands Operation: k PC< ...
Page 118
... PIC16C745/765 IORLW Inclusive OR Literal with W Syntax: [ label ] IORLW k Operands 255 Operation: (W) .OR. k (W) Status Affected: Z Description: The contents of the W register are OR’ed with the eight bit literal 'k'. The result is placed in the W register. IORWF Inclusive OR W with f Syntax: [ label ] IORWF f,d Operands: ...
Page 119
... PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction. 2000 Microchip Technology Inc. PIC16C745/765 RLF Rotate Left f through Carry Syntax: [ label ] Operands [0,1] Operation: ...
Page 120
... PIC16C745/765 SUBLW Subtract W from Literal Syntax: [ label ] SUBLW k Operands 255 Operation (W) W) Status Affected: C, DC, Z Description: The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register. SUBWF Subtract W from f Syntax: [ label ] SUBWF f,d Operands 127 ...
Page 121
... Customizable tool bar and key mapping • A status bar • On-line help 2000 Microchip Technology Inc. PIC16C745/765 MPLAB allows you to: • Edit your source files (either assembly or ‘C’) • One touch assemble (or compile) and download to PICmicro tools (automatically updates all project information) • ...
Page 122
... PIC16C745/765 15.4 MPLINK/MPLIB Linker/Librarian MPLINK is a relocatable linker for MPASM and MPLAB-C17 and MPLAB-C18. It can link relocatable objects from assembly or C source files along with pre- compiled libraries using directives from a linker script. MPLIB is a librarian for pre-compiled code to be used with MPLINK ...
Page 123
... Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB. 2000 Microchip Technology Inc. PIC16C745/765 15.12 PICDEM-2 Low-Cost PIC16CXX Demonstration Board The PICDEM simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers ...
Page 124
... PIC16C745/765 15.14 PICDEM-17 The PICDEM- evaluation board that demon- strates the capabilities of several Microchip microcon- trollers, including PIC17C752, PIC17C762, and PIC17C766. All necessary hardware is included to run basic demo programs, which are sup- plied on a 3.5-inch disk. A programmed sample is included, and the user may erase it and program it with ...
Page 125
... PIC16C6X á á á á PIC16C5X á á á PIC14000 á á á á PIC12CXXX Tools Software Emulators 2000 Microchip Technology Inc. PIC16C745/765 á á á á á á á á á á á á á á á á á á ...
Page 126
... PIC16C745/765 NOTES: DS41124C-page 126 Preliminary 2000 Microchip Technology Inc. ...
Page 127
... Maximum current sourced by PORTC and PORTD (Note 2) (combined).............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = V 2: PORTD and PORTE not available on the PIC16C745. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation list- ings of this specification is not implied ...
Page 128
... PIC16C745/765 FIGURE 16-1: VALID OPERATING REGIONS, FREQUENCY ON F -40°C TA +85°C 5.5 V 5.25 V 4.35 V 4.0 V DS41124C-page 128 , INT 24 MHz Frequency Preliminary 2000 Microchip Technology Inc. ...
Page 129
... DC Characteristics: PIC16C745/765 (Industrial) DC CHARACTERISTICS Param Sym Characteristic No. D001 V Supply Voltage DD D002* V RAM Data Retention DR Voltage (Note 1) D003 V V Start Voltage to ensure POR DD internal Power-on Reset signal D004 Rise Rate to ensure VDD DD D004A* internal Power-on Reset signal D005 V Brown-out Reset BOR ...
Page 130
... PIC16C745/765 16.2 DC Characteristics: PIC16C745/765 (Industrial) DC CHARACTERISTICS Param Sym Characteristic No. Input Low Voltage V I/O ports IL D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (in EC, E4 mode) D033 OSC1 (in HS, H4 mode) Input High Voltage V I/O ports IH D040 with TTL buffer ...
Page 131
... Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings Fall H High I Invalid (Hi-impedance) L Low 2000 Microchip Technology Inc. PIC16C745/765 T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z Hi-impedance Preliminary DS41124C-page 131 ...
Page 132
... PIC16C745/765 16.3.2 TIMING CONDITIONS The temperature and voltages specified in Table 16-1 apply to all timing specifications unless otherwise noted. Figure 16-2 specifies the load conditions for the timing specifications. TABLE 16-1: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ...
Page 133
... CLKIN F INT Note 1: F represents the internal clock signal. F INT equals CLKIN if the PLL is enabled. T OSC mode, PLL disabled OSC1 in EC mode with PLL disabled. INT 2000 Microchip Technology Inc. PIC16C745/765 equals F or CLKIN if the PLL is disabled. F INT OSC is always 4/F CY ...
Page 134
... PIC16C745/765 TABLE 16-2: EXTERNAL CLOCK TIMING REQUIREMENTS Param Sym Characteristic No External CLKIN Frequency OSC (Note 1) Oscillator Frequency (Note External CLKIN Period OSC (Note 1) Oscillator Period (Note Instruction Cycle Time (Note External Clock in (OSC1) High or Low Time External Clock in (OSC1) Rise or Fall ...
Page 135
... These parameters are for design guidance only and are not tested. ††These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in EC Mode where CLKOUT output OSC1 when PLL is disabled. INT 2000 Microchip Technology Inc. PIC16C745/765 ...
Page 136
... PIC16C745/765 FIGURE 16-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset I/O Pins Note: Refer to Figure 16-2 for load conditions. FIGURE 16-7: BROWN-OUT RESET TIMING V DD ...
Page 137
... Delay from external clock edge to timer increment TMR * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2000 Microchip Technology Inc. PIC16C745/765 ...
Page 138
... PIC16C745/765 FIGURE 16-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) CCPx (Capture Mode) CCPx (Compare or PWM Mode) Note: Refer to Figure 16-2 for load conditions. TABLE 16-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Param Sym Characteristic No. 50 CCP1 and CCP2 No Prescaler CC input low time With Prescaler ...
Page 139
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: PIC16C765 only. 2000 Microchip Technology Inc. PIC16C745/765 65 Characteristic Min Typ† ...
Page 140
... PIC16C745/765 FIGURE 16-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 RC7/RX/DT pin 120 Note: Refer to Figure 16-2 for load conditions. TABLE 16-8: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Sym No. 120 SYNC XMIT (MASTER & SLAVE Clock high to data out valid 121* ...
Page 141
... TABLE 16-10: A/D CONVERTER CHARACTERISTICS: PIC16C745/765 (INDUSTRIAL) Param Sym Characteristic No. A01 N Resolution R A02 E Total Absolute error ABS A03 E Integral linearity error IL A04 E Differential linearity error DL A05 E Full scale error FS A06 E Offset error OFF A10 — Monotonicity (Note 3) A20 V Reference voltage REF ...
Page 142
... PIC16C745/765 FIGURE 16-13: A/D CONVERSION TIMING BSF ADCON0, GO 134 (T /2) (1) OSC Q4 132 A/D CLK 7 A/D DATA ADRES ADIF GO SAMPLE Note: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. TABLE 16-11: A/D CONVERSION REQUIREMENTS Param Sym Characteristic No. ...
Page 143
... Voltage Output High OH V USB Voltage Output USB Note 1: Parameters are per USB Specification 1.1. No Microchip specific parameter numbers exist (per the PICmicro™ Mid-Range Reference Manual, DS33023. 2000 Microchip Technology Inc. PIC16C745/765 66.7ns 6MHz 60ns min 4.6V -1.0V 4ns min ...
Page 144
... PIC16C745/765 NOTES: DS41124C-page 144 Preliminary 2000 Microchip Technology Inc. ...
Page 145
... FIGURE 17-1: TYPICAL I vs 25.00 20.00 15.00 10.00 5.00 4.35 FIGURE 17-2: TYPICAL I vs 160.00 140.00 120.00 100.00 80.00 4.35 2000 Microchip Technology Inc 24MHz) DD INT 5.00 5.25 V (V) DD (USB SUSPENDED, WDT DISABLED) DD 5.00 5.25 V (V) DD Preliminary PIC16C745/765 DS41124C-page 145 ...
Page 146
... PIC16C745/765 FIGURE 17-3: DC LOAD LINES FOR USB REGULATOR OUTPUT ( Load Current (mA) DS41124C-page 146 USB Preliminary ) 2000 Microchip Technology Inc. ...
Page 147
... Standard OTP marking consists of Microchip part number, year code, week code and traceability code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2000 Microchip Technology Inc. PIC16C745/765 Example PIC16C745-I/SP 9917017 Example PIC16C745-I/SO 9917017 Example ...
Page 148
... XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead PLCC XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 40-Lead CERDIP Windowed XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN DS41124C-page 148 Example PIC16C765-I/P 9917017 Example PIC16C765-I/PT 9917017 Example PIC16C765-I/L 9917017 Example Preliminary PIC16C745-I/JW 9905017 2000 Microchip Technology Inc. ...
Page 149
... L .125 .130 .135 c .008 .012 .015 B1 .040 .053 .065 B .016 .019 .022 eB .320 .350 .430 Preliminary PIC16C745/765 MILLIMETERS MIN NOM MAX 28 2.54 3.56 3.81 4.06 3.18 3.30 3.43 0.38 7.62 7.87 8.26 6.99 7.24 7.49 34.16 34.67 35.18 3.18 3.30 3 ...
Page 150
... PIC16C745/765 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top ...
Page 151
... B1 .048 .050 .052 B .016 .018 .020 eB .296 .310 .324 W .161 .166 .171 T .490 .500 .510 U .275 .285 .295 Preliminary PIC16C745/765 MILLIMETERS MIN NOM MAX 28 2.54 3.94 4.48 5.03 2.92 3.43 3.94 1.02 1.27 1.52 7.11 7.37 7.62 35.20 35.56 35.92 3.30 3 ...
Page 152
... PIC16C745/765 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing § ...
Page 153
... L .135 .140 .145 c .008 .011 .014 B .050 .053 .055 B1 .016 .020 .023 eB .610 .660 .710 W .340 .350 .360 Preliminary PIC16C745/765 MILLIMETERS MIN NOM MAX 40 2.54 4.70 5.21 5.72 3.94 4.06 4.19 0.76 1.14 1.52 15.11 15.24 15.88 13.06 13.21 13.36 51.82 52 ...
Page 154
... PIC16C745/765 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP #leads= Dimension Limits Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff § Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width ...
Page 155
... E2 .590 .620 .630 D2 .590 .620 .630 c .008 .011 .013 B1 .026 .029 .032 B .013 .020 .021 Preliminary PIC16C745/765 MILLIMETERS MIN NOM MAX 44 1.27 11 4.19 4.39 4.57 3.68 3.87 4.06 0.51 0.71 0.89 0.61 0.74 0.86 1.02 1.14 1.27 0.00 0.13 ...
Page 156
... PIC16C745/765 NOTES: DS41124C-page 156 Preliminary 2000 Microchip Technology Inc. ...
Page 157
... Timer2 ....................................................................... 49 USART Receive ........................................................ 83 USART Transmit ....................................................... 81 Watchdog Timer ...................................................... 110 BOR bit ............................................................................ 103 BRGH bit ........................................................................... 79 Brown-out Reset (BOR) Timing Diagram ....................................................... 136 Buffer Descriptor Table ...................................................... 68 2000 Microchip Technology Inc. PIC16C745/765 C C bit ................................................................................... 22 Capture/Compare/PWM Capture Block Diagram ................................................... 53 CCP1CON Register .......................................... 52 CCP1IF ............................................................. 53 Mode ................................................................. 53 Prescaler ........................................................... 53 CCP Timer Resources .............................................. 51 Compare Block Diagram ...
Page 158
... PICDEM-2 Low-Cost PIC16CXX Demo Board ............... 123 PICDEM-3 Low-Cost PIC16CXXX Demo Board ............. 123 PICSTART Plus Entry Level Development System ..... 123 PIE1 Register .................................................................... 25 PIE2 Register .................................................................... 27 Pinout Descriptions PIC16C745/765 ......................................................... 11 PIR1 Register .................................................................... 26 PIR2 Register .................................................................... 27 POP ................................................................................... 29 POR ................................................................................ 103 Oscillator Start-up Timer (OST) ....................... 99 Power Control Register (PCON) ............................. 103 Power-on Reset (POR) ...
Page 159
... Timing Diagram ....................................................... 136 PR2 Register .............................................................. 18 PRO MATE II Universal Programmer ........................... 123 Product Identification System .......................................... 163 Program Counter PCLATH Register .................................................... 109 Program Memory Paging ....................................................................... 29 Program Memory Maps PIC16C745/765 ......................................................... 15 Program Verification ........................................................ 112 PSPMODE bit ...................................................... 37 PUSH ................................................................................. 29 R RBIF bit ..................................................................... 33 RCREG .............................................................................. 19 RCSTA Register ......................................................... 19 RD pin ................................................................................ 40 Register File ...................................................................... 15 ...
Page 160
... PIC16C745/765 USART Synchronous Transmission (Master/Slave) ......................................................... 140 Watchdog Timer (WDT) ........................................... 136 TMR0 ................................................................................. 20 TMR0 Register .................................................................. 17 TMR1CS bit ....................................................................... 45 TMR1H .............................................................................. 20 TMR1H Register ................................................................ 17 TMR1L ............................................................................... 20 TMR1L Register ................................................................ 17 TMR1ON bit ....................................................................... 45 TMR2 ................................................................................. 20 TMR2 Register .................................................................. 17 TMR2ON bit ....................................................................... 49 TO bit ................................................................................. 22 TOUTPS0 bit ..................................................................... 49 TOUTPS1 bit ..................................................................... 49 TOUTPS2 bit ..................................................................... 49 TOUTPS3 bit ..................................................................... 49 TRISA Register ........................................................... 18 TRISB Register ........................................................... 18 TRISC Register ...
Page 161
... Conferences for products, Development Systems, technical information and more • Listing of seminars and events 2000 Microchip Technology Inc. PIC16C745/765 Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. ...
Page 162
... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC16C745/765 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this data sheet easy to follow? If not, why? 4 ...
Page 163
... Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2000 Microchip Technology Inc. PIC16C745/765 XXX Examples: Pattern a) PIC16C745-I/P 301 = Industrial temp., PDIP package, QTP pattern #301. (2) (2) (Industrial) Note 1: C Note 2: T ...
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... Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system ...
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... Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan Microchip Technology Taiwan 11F-3, No. 207 ...